holes_module to be whitebox

diff --git a/passes/techmap/abc9_ops.cc b/passes/techmap/abc9_ops.cc
index 8eb935e1f11d6f73396ef6116719ad7071c1bf98..e65b16fc63667376da15849f81da87aef7de0cde 100644 (file)
--- a/passes/techmap/abc9_ops.cc
+++ b/passes/techmap/abc9_ops.cc
@@ -434,6 +434,8 @@ void prep_holes(RTLIL::Module *module)
        holes_design->modules_.erase(holes_module->name);
        holes_module->design = design;
 
+       holes_module->set_bool_attribute(ID::whitebox);
+
        log_pop();
 }
 
@@ -480,6 +482,14 @@ struct Abc9PrepPass : public Pass {
                extra_args(args, argidx, design);
 
                for (auto mod : design->selected_modules()) {
+                       if (mod->get_blackbox_attribute())
+                               continue;
+
+                       if (mod->processes.size() > 0) {
+                               log("Skipping module %s as it contains processes.\n", log_id(mod));
+                               continue;
+                       }
+
                        if (break_scc_mode)
                                break_scc(mod);
                        if (unbreak_scc_mode)