pysvp64asm: expand vector register macros

diff --git a/src/openpower/sv/trans/svp64.py b/src/openpower/sv/trans/svp64.py
index 29047b11ef3f1b26c194848d66afbc5597022d93..f242fe5cf4e5aa1a81bb894c1535a275402f93af 100644 (file)
--- a/src/openpower/sv/trans/svp64.py
+++ b/src/openpower/sv/trans/svp64.py
@@ -796,7 +796,7 @@ class SVP64Asm:
         svp64 = self.svp64
         insn_no_comments = insn.partition('#')[0]
         # find first space, to get opcode
-        ls = insn_no_comments.split(' ')
+        ls = insn_no_comments.split()
         opcode = ls[0]
         # now find opcode fields
         fields = ''.join(ls[1:]).split(',')
@@ -1491,6 +1491,13 @@ def macro_subst(macros, txt):
                 log("macro", txt, "replaced", replaced, toreplace, value)
                 txt = replaced
                 continue
+            toreplace = '*%s' % macro
+            if toreplace in txt:
+                again = True
+                replaced = txt.replace(toreplace, '*%s' % value)
+                log("macro", txt, "replaced", replaced, toreplace, value)
+                txt = replaced
+                continue
             toreplace = '(%s)' % macro
             if toreplace in txt:
                 again = True