corelogic -> genlib

diff --git a/mibuild/generic_platform.py b/mibuild/generic_platform.py
index aabd1a07f092b60469435bda50876162b9c1c0fc..6777e76588a46c17e471a4e67250394740d7fa1f 100644 (file)
--- a/mibuild/generic_platform.py
+++ b/mibuild/generic_platform.py
@@ -2,7 +2,7 @@ from copy import copy
 import os, argparse
 
 from migen.fhdl.structure import *
-from migen.corelogic.record import Record
+from migen.genlib.record import Record
 from migen.fhdl import verilog
 
 from mibuild import tools