+2011-05-18 Stuart Henderson <shenders@gcc.gnu.org>
+
+ * doc/invoke.texi (Blackfin Options): -mcpu accepts bf592.
+ * config/bfin/t-bfin-elf (MULTILIB_MATCHES): Select bf532-none for
+ bf592-none.
+ * config/bfin/t-bfin-linux (MULTILIB_MATCHES): Likewise.
+ * config/bfin/t-bfin-uclinux (MULTILIB_MATCHES): Likewise.
+ * config/bfin/bfin.c (bfin_cpus): Add bf592.
+ * config/bfin/bfin.h (TARGET_CPU_CPP_BUILTINS): Define
+ __ADSPBF592__ and __ADSPBF59x__ for BFIN_CPU_BF592.
+ * config/bfin/bfin-opts.h (bfin_cpu_type): Add BFIN_CPU_BF592.
+ * config/bfin/elf.h (LIB_SPEC): Add bf592.
+
2011-05-18 Joseph Myers <joseph@codesourcery.com>
* config/arm/arm-opts.h (enum arm_fp16_format_type, enum
BFIN_CPU_BF548M,
BFIN_CPU_BF549,
BFIN_CPU_BF549M,
- BFIN_CPU_BF561
+ BFIN_CPU_BF561,
+ BFIN_CPU_BF592
} bfin_cpu_t;
#endif
| WA_05000283 | WA_05000257 | WA_05000315 | WA_LOAD_LCREGS
| WA_05000074},
+ {"bf592", BFIN_CPU_BF592, 0x0001,
+ WA_SPECULATIVE_LOADS | WA_05000074},
+ {"bf592", BFIN_CPU_BF592, 0x0000,
+ WA_SPECULATIVE_LOADS | WA_05000074},
+
{NULL, BFIN_CPU_UNKNOWN, 0, 0}
};
case BFIN_CPU_BF561: \
builtin_define ("__ADSPBF561__"); \
break; \
+ case BFIN_CPU_BF592: \
+ builtin_define ("__ADSPBF592__"); \
+ builtin_define ("__ADSPBF59x__"); \
+ break; \
} \
\
if (bfin_si_revision != -1) \
%{mmulticore:%{mcorea:-T bf561a.ld%s}} \
%{mmulticore:%{mcoreb:-T bf561b.ld%s}} \
%{mmulticore:%{!mcorea:%{!mcoreb:-T bf561m.ld%s}}}} \
+ %{mcpu=bf592*:-T bf592.ld%s} \
%{!mcpu=*:%eno processor type specified for linking} \
%{!mcpu=bf561*:-T bfin-common-sc.ld%s} \
%{mcpu=bf561*:%{!mmulticore:-T bfin-common-sc.ld%s} \
MULTILIB_MATCHES+=mcpu?bf532-none=mcpu?bf549-none
MULTILIB_MATCHES+=mcpu?bf532-none=mcpu?bf549m-none
MULTILIB_MATCHES+=mcpu?bf532-none=mcpu?bf561-none
+MULTILIB_MATCHES+=mcpu?bf532-none=mcpu?bf592-none
MULTILIB_EXCEPTIONS=mleaf-id-shared-library*
MULTILIB_EXCEPTIONS+=mcpu=bf532-none/mleaf-id-shared-library*
MULTILIB_MATCHES+=mcpu?bf532-none=mcpu?bf549-none
MULTILIB_MATCHES+=mcpu?bf532-none=mcpu?bf549m-none
MULTILIB_MATCHES+=mcpu?bf532-none=mcpu?bf561-none
+MULTILIB_MATCHES+=mcpu?bf532-none=mcpu?bf592-none
SHLIB_MAPFILES=$(srcdir)/config/bfin/libgcc-bfin.ver
MULTILIB_MATCHES+=mcpu?bf532-none=mcpu?bf549-none
MULTILIB_MATCHES+=mcpu?bf532-none=mcpu?bf549m-none
MULTILIB_MATCHES+=mcpu?bf532-none=mcpu?bf561-none
+MULTILIB_MATCHES+=mcpu?bf532-none=mcpu?bf592-none
MULTILIB_EXCEPTIONS=mleaf-id-shared-library*
MULTILIB_EXCEPTIONS+=mcpu=bf532-none/mleaf-id-shared-library*
@samp{bf534}, @samp{bf536}, @samp{bf537}, @samp{bf538}, @samp{bf539},
@samp{bf542}, @samp{bf544}, @samp{bf547}, @samp{bf548}, @samp{bf549},
@samp{bf542m}, @samp{bf544m}, @samp{bf547m}, @samp{bf548m}, @samp{bf549m},
-@samp{bf561}.
+@samp{bf561}, @samp{bf592}.
The optional @var{sirevision} specifies the silicon revision of the target
Blackfin processor. Any workarounds available for the targeted silicon revision
will be enabled. If @var{sirevision} is @samp{none}, no workarounds are enabled.