(no commit message)

diff --git a/openpower/sv/SimpleV_rationale.mdwn b/openpower/sv/SimpleV_rationale.mdwn
index 4afb0c3926bb41c37cd0415e8d9142da4027b3e6..85116acede6f16acaf91d9b45ba047849655475c 100644 (file)
--- a/openpower/sv/SimpleV_rationale.mdwn
+++ b/openpower/sv/SimpleV_rationale.mdwn
@@ -241,13 +241,13 @@ of magnitude increase in the number of hand-written lines of assembler
 compared to a well-designed Cray-style Vector ISA with a `setvl`
 instruction.
 
-<blockquote>
-*Packed SIMD looped algorithms actually have to
+*<blockquote>
+Packed SIMD looped algorithms actually have to
 contain multiple implementations processing fragments of data at
 different SIMD widths: Cray-style Vectors have just the one, covering not
 just current architectural implementations but future ones with
-wider back-end ALUs as well.*
-</blockquote>
+wider back-end ALUs as well.
+</blockquote>*
 
 Assuming then that variable-length Vectors are obviously desirable,
 it becomes a matter of how, not if.  Both Cray and NEC SX Aurora