(FILE *, rtx);
static void frv_print_operand_memory_reference (FILE *, rtx, int);
static int frv_print_operand_jump_hint (rtx);
+static const char *comparison_string (enum rtx_code, rtx);
static FRV_INLINE int frv_regno_ok_for_base_p (int, int);
static rtx single_set_pattern (rtx);
static int frv_function_contains_far_jump (void);
}
\f
+/* Return the comparison operator to use for CODE given that the ICC
+ register is OP0. */
+
+static const char *
+comparison_string (enum rtx_code code, rtx op0)
+{
+ bool is_nz_p = GET_MODE (op0) == CC_NZmode;
+ switch (code)
+ {
+ default: output_operand_lossage ("bad condition code");
+ case EQ: return "eq";
+ case NE: return "ne";
+ case LT: return is_nz_p ? "n" : "lt";
+ case LE: return "le";
+ case GT: return "gt";
+ case GE: return is_nz_p ? "p" : "ge";
+ case LTU: return is_nz_p ? "no" : "c";
+ case LEU: return is_nz_p ? "eq" : "ls";
+ case GTU: return is_nz_p ? "ne" : "hi";
+ case GEU: return is_nz_p ? "ra" : "nc";
+ }
+}
+
/* Print an operand to an assembler instruction.
`%' followed by a letter and a digit says to output an operand in an
case 'C':
/* Print appropriate test for integer branch false operation. */
- switch (GET_CODE (x))
- {
- default:
- fatal_insn ("Bad insn to frv_print_operand, 'C' modifier:", x);
-
- case EQ: fputs ("ne", file); break;
- case NE: fputs ("eq", file); break;
- case LT: fputs ("ge", file); break;
- case LE: fputs ("gt", file); break;
- case GT: fputs ("le", file); break;
- case GE: fputs ("lt", file); break;
- case LTU: fputs ("nc", file); break;
- case LEU: fputs ("hi", file); break;
- case GTU: fputs ("ls", file); break;
- case GEU: fputs ("c", file); break;
- }
+ fputs (comparison_string (reverse_condition (GET_CODE (x)),
+ XEXP (x, 0)), file);
break;
- /* case 'c': print a constant without the constant prefix. If
- CONSTANT_ADDRESS_P(x) is not true, PRINT_OPERAND is called. */
-
case 'c':
/* Print appropriate test for integer branch true operation. */
- switch (GET_CODE (x))
- {
- default:
- fatal_insn ("Bad insn to frv_print_operand, 'c' modifier:", x);
-
- case EQ: fputs ("eq", file); break;
- case NE: fputs ("ne", file); break;
- case LT: fputs ("lt", file); break;
- case LE: fputs ("le", file); break;
- case GT: fputs ("gt", file); break;
- case GE: fputs ("ge", file); break;
- case LTU: fputs ("c", file); break;
- case LEU: fputs ("ls", file); break;
- case GTU: fputs ("hi", file); break;
- case GEU: fputs ("nc", file); break;
- }
+ fputs (comparison_string (GET_CODE (x), XEXP (x, 0)), file);
break;
case 'e':
int
relational_operator (rtx op, enum machine_mode mode)
{
- rtx op0;
- rtx op1;
- int regno;
-
- if (mode != VOIDmode && mode != GET_MODE (op))
- return FALSE;
-
- switch (GET_CODE (op))
- {
- default:
- return FALSE;
-
- case EQ:
- case NE:
- case LE:
- case LT:
- case GE:
- case GT:
- case LEU:
- case LTU:
- case GEU:
- case GTU:
- break;
- }
-
- op1 = XEXP (op, 1);
- if (op1 != const0_rtx)
- return FALSE;
-
- op0 = XEXP (op, 0);
- if (GET_CODE (op0) != REG)
- return FALSE;
-
- regno = REGNO (op0);
- switch (GET_MODE (op0))
- {
- default:
- break;
-
- case CCmode:
- case CC_UNSmode:
- return ICC_OR_PSEUDO_P (regno);
-
- case CC_FPmode:
- return FCC_OR_PSEUDO_P (regno);
-
- case CC_CCRmode:
- return CR_OR_PSEUDO_P (regno);
- }
-
- return FALSE;
+ return (integer_relational_operator (op, mode)
+ || float_relational_operator (op, mode));
}
-/* Return true if operator is a signed integer relational operator. */
+/* Return true if OP is a relational operator suitable for CCmode,
+ CC_UNSmode or CC_NZmode. */
int
-signed_relational_operator (rtx op, enum machine_mode mode)
+integer_relational_operator (rtx op, enum machine_mode mode)
{
- rtx op0;
- rtx op1;
- int regno;
-
if (mode != VOIDmode && mode != GET_MODE (op))
return FALSE;
+ /* The allowable relations depend on the mode of the ICC register. */
switch (GET_CODE (op))
{
default:
case EQ:
case NE:
- case LE:
case LT:
case GE:
- case GT:
- break;
- }
+ return (GET_MODE (XEXP (op, 0)) == CC_NZmode
+ || GET_MODE (XEXP (op, 0)) == CCmode);
- op1 = XEXP (op, 1);
- if (op1 != const0_rtx)
- return FALSE;
-
- op0 = XEXP (op, 0);
- if (GET_CODE (op0) != REG)
- return FALSE;
-
- regno = REGNO (op0);
- if (GET_MODE (op0) == CCmode && ICC_OR_PSEUDO_P (regno))
- return TRUE;
-
- if (GET_MODE (op0) == CC_CCRmode && CR_OR_PSEUDO_P (regno))
- return TRUE;
-
- return FALSE;
-}
-
-/* Return true if operator is a signed integer relational operator. */
-
-int
-unsigned_relational_operator (rtx op, enum machine_mode mode)
-{
- rtx op0;
- rtx op1;
- int regno;
-
- if (mode != VOIDmode && mode != GET_MODE (op))
- return FALSE;
-
- switch (GET_CODE (op))
- {
- default:
- return FALSE;
+ case LE:
+ case GT:
+ return GET_MODE (XEXP (op, 0)) == CCmode;
- case LEU:
- case LTU:
- case GEU:
case GTU:
- break;
+ case GEU:
+ case LTU:
+ case LEU:
+ return (GET_MODE (XEXP (op, 0)) == CC_NZmode
+ || GET_MODE (XEXP (op, 0)) == CC_UNSmode);
}
-
- op1 = XEXP (op, 1);
- if (op1 != const0_rtx)
- return FALSE;
-
- op0 = XEXP (op, 0);
- if (GET_CODE (op0) != REG)
- return FALSE;
-
- regno = REGNO (op0);
- if (GET_MODE (op0) == CC_UNSmode && ICC_OR_PSEUDO_P (regno))
- return TRUE;
-
- if (GET_MODE (op0) == CC_CCRmode && CR_OR_PSEUDO_P (regno))
- return TRUE;
-
- return FALSE;
}
/* Return true if operator is a floating point relational operator. */
int
float_relational_operator (rtx op, enum machine_mode mode)
{
- rtx op0;
- rtx op1;
- int regno;
-
if (mode != VOIDmode && mode != GET_MODE (op))
return FALSE;
case ORDERED:
case UNORDERED:
#endif
- break;
+ return GET_MODE (XEXP (op, 0)) == CC_FPmode;
}
-
- op1 = XEXP (op, 1);
- if (op1 != const0_rtx)
- return FALSE;
-
- op0 = XEXP (op, 0);
- if (GET_CODE (op0) != REG)
- return FALSE;
-
- regno = REGNO (op0);
- if (GET_MODE (op0) == CC_FPmode && FCC_OR_PSEUDO_P (regno))
- return TRUE;
-
- if (GET_MODE (op0) == CC_CCRmode && CR_OR_PSEUDO_P (regno))
- return TRUE;
-
- return FALSE;
}
/* Return true if operator is EQ/NE of a conditional execution register. */
return frv_legitimate_address_p (mode, addr, reload_completed, TRUE, FALSE);
}
-/* Return true if operator is an integer binary operator that can be combined
- with a setcc operation. Do not allow the arithmetic operations that could
- potentially overflow since the FR-V sets the condition code based on the
- "true" value of the result, not the result after truncating to a 32-bit
- register. */
+/* Return true if OP is an integer binary operator that can be combined
+ with a (set ... (compare:CC_NZ ...)) pattern. */
int
intop_compare_operator (rtx op, enum machine_mode mode)
{
- enum machine_mode op_mode = GET_MODE (op);
-
- if (mode != VOIDmode && op_mode != mode)
- return FALSE;
-
- switch (GET_CODE (op))
- {
- default:
- return FALSE;
-
- case AND:
- case IOR:
- case XOR:
- case ASHIFTRT:
- case LSHIFTRT:
- break;
- }
-
- if (! integer_register_operand (XEXP (op, 0), SImode))
- return FALSE;
-
- if (! gpr_or_int10_operand (XEXP (op, 1), SImode))
- return FALSE;
-
- return TRUE;
-}
-
-/* Return true if operator is an integer binary operator that can be combined
- with a setcc operation inside of a conditional execution. */
-
-int
-condexec_intop_cmp_operator (rtx op, enum machine_mode mode)
-{
- enum machine_mode op_mode = GET_MODE (op);
-
- if (mode != VOIDmode && op_mode != mode)
+ if (mode != VOIDmode && GET_MODE (op) != mode)
return FALSE;
switch (GET_CODE (op))
default:
return FALSE;
+ case PLUS:
+ case MINUS:
case AND:
case IOR:
case XOR:
case ASHIFTRT:
case LSHIFTRT:
- break;
+ return GET_MODE (op) == SImode;
}
-
- if (! integer_register_operand (XEXP (op, 0), SImode))
- return FALSE;
-
- if (! integer_register_operand (XEXP (op, 1), SImode))
- return FALSE;
-
- return TRUE;
}
/* Return 1 if operand is a valid ACC register number. */
/* Allocate the appropriate temporary condition code register. Try to
allocate the ICR/FCR register that corresponds to the ICC/FCC register so
that conditional cmp's can be done. */
- if (mode == CCmode || mode == CC_UNSmode)
+ if (mode == CCmode || mode == CC_UNSmode || mode == CC_NZmode)
{
cr_class = ICR_REGS;
cc_class = ICC_REGS;
if (GET_CODE (cr) != REG)
goto fail;
- if (mode == CCmode || mode == CC_UNSmode)
+ if (mode == CCmode || mode == CC_UNSmode || mode == CC_NZmode)
{
cr_class = ICR_REGS;
p_new_cr = &frv_ifcvt.extra_int_cr;
{
case CCmode:
case CC_UNSmode:
+ case CC_NZmode:
return ICC_P (regno) || GPR_P (regno);
case CC_CCRmode:
/* Otherwise store the constant away and do a load. */
return FALSE;
}
+
+/* Implement SELECT_CC_MODE. Choose CC_FP for floating-point comparisons,
+ CC_NZ for comparisons against zero in which a single Z or N flag test
+ is enough, CC_UNS for other unsigned comparisons, and CC for other
+ signed comparisons. */
+
+enum machine_mode
+frv_select_cc_mode (enum rtx_code code, rtx x, rtx y)
+{
+ if (GET_MODE_CLASS (GET_MODE (x)) == MODE_FLOAT)
+ return CC_FPmode;
+
+ switch (code)
+ {
+ case EQ:
+ case NE:
+ case LT:
+ case GE:
+ return y == const0_rtx ? CC_NZmode : CCmode;
+
+ case GTU:
+ case GEU:
+ case LTU:
+ case LEU:
+ return y == const0_rtx ? CC_NZmode : CC_UNSmode;
+
+ default:
+ return CCmode;
+ }
+}
\f
/* A C expression for the cost of moving data from a register in class FROM to
one in class TO. The classes are expressed using the enumeration values
""
"operands[3] = gen_rtx_REG (CC_CCRmode, ICR_TEMP);")
+;; Reload CC_NZmode. This is mostly the same as the CCmode and CC_UNSmode
+;; handling, but it uses different sequences for moving between GPRs and ICCs.
+
+(define_expand "movcc_nz"
+ [(parallel [(set (match_operand:CC_NZ 0 "move_destination_operand" "")
+ (match_operand:CC_NZ 1 "move_source_operand" ""))
+ (clobber (match_dup 2))])]
+ ""
+ "
+{
+ if (!reload_in_progress && !reload_completed)
+ FAIL;
+ operands[2] = gen_rtx_REG (CC_CCRmode, ICR_TEMP);
+}")
+
+(define_insn "*internal_movcc_nz"
+ [(set (match_operand:CC_NZ 0 "move_destination_operand" "=t,d,d,m,d")
+ (match_operand:CC_NZ 1 "move_source_operand" "d,d,m,d,t"))
+ (clobber (match_scratch:CC_CCR 2 "=X,X,X,X,&v"))]
+ "reload_in_progress || reload_completed"
+ "@
+ cmpi %1, #0, %0
+ mov %1, %0
+ ld%I1%U1 %M1, %0
+ st%I0%U0 %1, %M0
+ #"
+ [(set_attr "length" "4,4,4,4,20")
+ (set_attr "type" "int,int,gload,gstore,multi")])
+
+;; Set the destination to a value that, when compared with zero, will
+;; restore the value of the Z and N flags. The values of the other
+;; flags don't matter. The sequence is:
+;;
+;; setlos op0,#-1
+;; ckp op1,op2
+;; csub gr0,op0,op0,op2
+;; ckeq op1,op2
+;; cmov gr0,op0,op2
+(define_split
+ [(set (match_operand:CC_NZ 0 "integer_register_operand" "")
+ (match_operand:CC_NZ 1 "icc_operand" ""))
+ (clobber (match_operand:CC_CCR 2 "icr_operand" ""))]
+ "reload_in_progress || reload_completed"
+ [(set (match_dup 3)
+ (const_int -1))
+ (set (match_dup 2)
+ (ge:CC_CCR (match_dup 1)
+ (const_int 0)))
+ (cond_exec (ne:CC_CCR (match_dup 2)
+ (const_int 0))
+ (set (match_dup 3)
+ (neg:SI (match_dup 3))))
+ (set (match_dup 2)
+ (eq:CC_CCR (match_dup 1)
+ (const_int 0)))
+ (cond_exec (ne:CC_CCR (match_dup 2)
+ (const_int 0))
+ (set (match_dup 3) (const_int 0)))]
+ "operands[3] = simplify_gen_subreg (SImode, operands[0], CC_NZmode, 0);")
+
+(define_expand "reload_incc_nz"
+ [(parallel [(set (match_operand:CC_NZ 2 "integer_register_operand" "=&d")
+ (match_operand:CC_NZ 1 "memory_operand" "m"))
+ (clobber (match_scratch:CC_CCR 3 ""))])
+ (parallel [(set (match_operand:CC_NZ 0 "icc_operand" "=t")
+ (match_dup 2))
+ (clobber (match_scratch:CC_CCR 4 ""))])]
+ ""
+ "")
+
+(define_expand "reload_outcc_nz"
+ [(parallel [(set (match_operand:CC_NZ 2 "integer_register_operand" "=&d")
+ (match_operand:CC_NZ 1 "icc_operand" "t"))
+ (clobber (match_dup 3))])
+ (parallel [(set (match_operand:CC_NZ 0 "memory_operand" "=m")
+ (match_dup 2))
+ (clobber (match_scratch:CC_CCR 4 ""))])]
+ ""
+ "operands[3] = gen_rtx_REG (CC_CCRmode, ICR_TEMP);")
+
;; Reload CC_FPmode for floating point comparisons
;; We use a define_expand here so that cse/gcse/combine can't accidentally
;; create movcc insns. If this was a named define_insn, we would not be able
;; ::::::::::::::::::::
(define_insn "*combo_intop_compare1"
- [(set (match_operand:CC 0 "icc_operand" "=t")
- (compare:CC (match_operator:SI 1 "intop_compare_operator"
- [(match_operand:SI 2 "integer_register_operand" "d")
- (match_operand:SI 3 "gpr_or_int10_operand" "dJ")])
- (const_int 0)))]
+ [(set (match_operand:CC_NZ 0 "icc_operand" "=t")
+ (compare:CC_NZ
+ (match_operator:SI 1 "intop_compare_operator"
+ [(match_operand:SI 2 "integer_register_operand" "d")
+ (match_operand:SI 3 "gpr_or_int10_operand" "dJ")])
+ (const_int 0)))]
""
"%O1%I3cc %2, %3, %., %0"
[(set_attr "type" "int")
(set_attr "length" "4")])
(define_insn "*combo_intop_compare2"
- [(set (match_operand:CC_UNS 0 "icc_operand" "=t")
- (compare:CC_UNS (match_operator:SI 1 "intop_compare_operator"
- [(match_operand:SI 2 "integer_register_operand" "d")
- (match_operand:SI 3 "gpr_or_int10_operand" "dJ")])
- (const_int 0)))]
- ""
- "%O1%I3cc %2, %3, %., %0"
- [(set_attr "type" "int")
- (set_attr "length" "4")])
-
-(define_insn "*combo_intop_compare3"
- [(set (match_operand:CC 0 "icc_operand" "=t")
- (compare:CC (match_operator:SI 1 "intop_compare_operator"
- [(match_operand:SI 2 "integer_register_operand" "d")
- (match_operand:SI 3 "gpr_or_int10_operand" "dJ")])
- (const_int 0)))
- (set (match_operand:SI 4 "integer_register_operand" "=d")
- (match_operator:SI 5 "intop_compare_operator"
- [(match_dup 2)
- (match_dup 3)]))]
- "GET_CODE (operands[1]) == GET_CODE (operands[5])"
- "%O1%I3cc %2, %3, %4, %0"
- [(set_attr "type" "int")
- (set_attr "length" "4")])
-
-(define_insn "*combo_intop_compare4"
- [(set (match_operand:CC_UNS 0 "icc_operand" "=t")
- (compare:CC_UNS (match_operator:SI 1 "intop_compare_operator"
- [(match_operand:SI 2 "integer_register_operand" "d")
- (match_operand:SI 3 "gpr_or_int10_operand" "dJ")])
- (const_int 0)))
+ [(set (match_operand:CC_NZ 0 "icc_operand" "=t")
+ (compare:CC_NZ
+ (match_operator:SI 1 "intop_compare_operator"
+ [(match_operand:SI 2 "integer_register_operand" "d")
+ (match_operand:SI 3 "gpr_or_int10_operand" "dJ")])
+ (const_int 0)))
(set (match_operand:SI 4 "integer_register_operand" "=d")
(match_operator:SI 5 "intop_compare_operator"
[(match_dup 2)
"%O1%I3cc %2, %3, %4, %0"
[(set_attr "type" "int")
(set_attr "length" "4")])
-
\f
;; ::::::::::::::::::::
;; ::
[(set_attr "length" "4")
(set_attr "type" "int")])
+;; The only requirement for a CC_NZmode GPR or memory value is that
+;; comparing it against zero must set the Z and N flags appropriately.
+;; The source operand is therefore a valid CC_NZmode value.
+(define_insn "*cmpsi_cc_nz"
+ [(set (match_operand:CC_NZ 0 "nonimmediate_operand" "=t,d,m")
+ (compare:CC_NZ (match_operand:SI 1 "integer_register_operand" "d,d,d")
+ (const_int 0)))]
+ ""
+ "@
+ cmpi %1, #0, %0
+ mov %1, %0
+ st%I0%U0 %1, %M0"
+ [(set_attr "length" "4,4,4")
+ (set_attr "type" "int,int,gstore")])
+
(define_insn "*cmpsf_cc_fp"
[(set (match_operand:CC_FP 0 "fcc_operand" "=u")
(compare:CC_FP (match_operand:SF 1 "fpr_operand" "f")
;; In the above example the %B is a directive to frv_print_operand()
;; to decode and print the correct branch mnemonic.
-(define_insn "*branch_signed_true"
- [(set (pc)
- (if_then_else (match_operator:CC 0 "signed_relational_operator"
- [(match_operand 1 "icc_operand" "t")
- (const_int 0)])
- (label_ref (match_operand 2 "" ""))
- (pc)))]
- ""
- "*
-{
- if (get_attr_length (insn) == 4)
- return \"b%c0 %1,%#,%l2\";
- else
- return \"b%C0 %1,%#,1f\;call %l2\\n1:\";
-}"
- [(set (attr "length")
- (if_then_else
- (and (ge (minus (match_dup 2) (pc)) (const_int -32768))
- (le (minus (match_dup 2) (pc)) (const_int 32764)))
- (const_int 4)
- (const_int 8)))
- (set (attr "far_jump")
- (if_then_else
- (eq_attr "length" "4")
- (const_string "no")
- (const_string "yes")))
- (set (attr "type")
- (if_then_else
- (eq_attr "length" "4")
- (const_string "branch")
- (const_string "multi")))])
-
-(define_insn "*branch_signed_false"
- [(set (pc)
- (if_then_else (match_operator:CC 0 "signed_relational_operator"
- [(match_operand 1 "icc_operand" "t")
- (const_int 0)])
- (pc)
- (label_ref (match_operand 2 "" ""))))]
- ""
- "*
-{
- if (get_attr_length (insn) == 4)
- return \"b%C0 %1,%#,%l2\";
- else
- return \"b%c0 %1,%#,1f\;call %l2\\n1:\";
-}"
- [(set (attr "length")
- (if_then_else
- (and (ge (minus (match_dup 2) (pc)) (const_int -32768))
- (le (minus (match_dup 2) (pc)) (const_int 32764)))
- (const_int 4)
- (const_int 8)))
- (set (attr "far_jump")
- (if_then_else
- (eq_attr "length" "4")
- (const_string "no")
- (const_string "yes")))
- (set (attr "type")
- (if_then_else
- (eq_attr "length" "4")
- (const_string "branch")
- (const_string "multi")))])
-
-(define_insn "*branch_unsigned_true"
+(define_insn "*branch_int_true"
[(set (pc)
- (if_then_else (match_operator:CC_UNS 0 "unsigned_relational_operator"
- [(match_operand 1 "icc_operand" "t")
- (const_int 0)])
+ (if_then_else (match_operator 0 "integer_relational_operator"
+ [(match_operand 1 "icc_operand" "t")
+ (const_int 0)])
(label_ref (match_operand 2 "" ""))
(pc)))]
""
(const_string "branch")
(const_string "multi")))])
-(define_insn "*branch_unsigned_false"
+(define_insn "*branch_int_false"
[(set (pc)
- (if_then_else (match_operator:CC_UNS 0 "unsigned_relational_operator"
- [(match_operand 1 "icc_operand" "t")
- (const_int 0)])
+ (if_then_else (match_operator 0 "integer_relational_operator"
+ [(match_operand 1 "icc_operand" "t")
+ (const_int 0)])
(pc)
(label_ref (match_operand 2 "" ""))))]
""
DONE;
}")
-(define_insn "*scc_signed"
- [(set (match_operand:SI 0 "integer_register_operand" "=d")
- (match_operator:SI 1 "signed_relational_operator"
- [(match_operand:CC 2 "icc_operand" "t")
- (const_int 0)]))
- (clobber (match_operand:CC_CCR 3 "icr_operand" "=v"))]
- ""
- "#"
- [(set_attr "length" "12")
- (set_attr "type" "multi")])
-
-(define_insn "*scc_unsigned"
+(define_insn "*scc_int"
[(set (match_operand:SI 0 "integer_register_operand" "=d")
- (match_operator:SI 1 "unsigned_relational_operator"
- [(match_operand:CC_UNS 2 "icc_operand" "t")
+ (match_operator:SI 1 "integer_relational_operator"
+ [(match_operand 2 "icc_operand" "t")
(const_int 0)]))
(clobber (match_operand:CC_CCR 3 "icr_operand" "=v"))]
""
"operands[4] = frv_split_scc (operands[0], operands[1], operands[2],
operands[3], (HOST_WIDE_INT) 1);")
-(define_insn "*scc_neg1_signed"
+(define_insn "*scc_neg1_int"
[(set (match_operand:SI 0 "integer_register_operand" "=d")
- (neg:SI (match_operator:SI 1 "signed_relational_operator"
- [(match_operand:CC 2 "icc_operand" "t")
- (const_int 0)])))
- (clobber (match_operand:CC_CCR 3 "icr_operand" "=v"))]
- ""
- "#"
- [(set_attr "length" "12")
- (set_attr "type" "multi")])
-
-(define_insn "*scc_neg1_unsigned"
- [(set (match_operand:SI 0 "integer_register_operand" "=d")
- (neg:SI (match_operator:SI 1 "unsigned_relational_operator"
- [(match_operand:CC_UNS 2 "icc_operand" "t")
+ (neg:SI (match_operator:SI 1 "integer_relational_operator"
+ [(match_operand 2 "icc_operand" "t")
(const_int 0)])))
(clobber (match_operand:CC_CCR 3 "icr_operand" "=v"))]
""
;; Convert ICC/FCC comparison into CCR bits so we can do conditional execution
(define_insn "*ck_signed"
[(set (match_operand:CC_CCR 0 "icr_operand" "=v")
- (match_operator:CC_CCR 1 "signed_relational_operator"
- [(match_operand:CC 2 "icc_operand" "t")
- (const_int 0)]))]
- ""
- "ck%c1 %2, %0"
- [(set_attr "length" "4")
- (set_attr "type" "ccr")])
-
-(define_insn "*ck_unsigned"
- [(set (match_operand:CC_CCR 0 "icr_operand" "=v")
- (match_operator:CC_CCR 1 "unsigned_relational_operator"
- [(match_operand:CC_UNS 2 "icc_operand" "t")
+ (match_operator:CC_CCR 1 "integer_relational_operator"
+ [(match_operand 2 "icc_operand" "t")
(const_int 0)]))]
""
"ck%c1 %2, %0"
[(set_attr "length" "4")
(set_attr "type" "int")])
+(define_insn "*cond_exec_cmpsi_cc_nz"
+ [(cond_exec
+ (match_operator 0 "ccr_eqne_operator"
+ [(match_operand 1 "cr_operand" "C")
+ (const_int 0)])
+ (set (match_operand:CC_NZ 2 "icc_operand" "=t")
+ (compare:CC_NZ (match_operand:SI 3 "integer_register_operand" "d")
+ (const_int 0))))]
+ "reload_completed
+ && REGNO (operands[1]) == REGNO (operands[2]) - ICC_FIRST + ICR_FIRST"
+ "ccmp %3, %., %1, %e0"
+ [(set_attr "length" "4")
+ (set_attr "type" "int")])
+
(define_insn "*cond_exec_sf_conv"
[(cond_exec
(match_operator 0 "ccr_eqne_operator"
DONE;
}")
-(define_insn "*movqicc_internal1_signed"
- [(set (match_operand:QI 0 "integer_register_operand" "=d,d,d")
- (if_then_else:QI (match_operator:CC 1 "signed_relational_operator"
- [(match_operand:CC 2 "icc_operand" "t,t,t")
- (const_int 0)])
- (match_operand:QI 3 "reg_or_0_operand" "0,dO,dO")
- (match_operand:QI 4 "reg_or_0_operand" "dO,0,dO")))
- (clobber (match_operand:CC_CCR 5 "icr_operand" "=v,v,v"))]
- ""
- "#"
- [(set_attr "length" "8,8,12")
- (set_attr "type" "multi")])
-
-(define_insn "*movqicc_internal1_unsigned"
+(define_insn "*movqicc_internal1_int"
[(set (match_operand:QI 0 "integer_register_operand" "=d,d,d")
- (if_then_else:QI (match_operator:CC_UNS 1 "unsigned_relational_operator"
- [(match_operand:CC_UNS 2 "icc_operand" "t,t,t")
+ (if_then_else:QI (match_operator 1 "integer_relational_operator"
+ [(match_operand 2 "icc_operand" "t,t,t")
(const_int 0)])
(match_operand:QI 3 "reg_or_0_operand" "0,dO,dO")
(match_operand:QI 4 "reg_or_0_operand" "dO,0,dO")))
[(set_attr "length" "8,8,12")
(set_attr "type" "multi")])
-(define_insn "*movqicc_internal2_signed"
- [(set (match_operand:QI 0 "integer_register_operand" "=d,d,d,d,d")
- (if_then_else:QI (match_operator:CC 1 "signed_relational_operator"
- [(match_operand:CC 2 "icc_operand" "t,t,t,t,t")
- (const_int 0)])
- (match_operand:QI 3 "const_int_operand" "O,O,L,n,n")
- (match_operand:QI 4 "const_int_operand" "L,n,O,O,n")))
- (clobber (match_operand:CC_CCR 5 "icr_operand" "=v,v,v,v,v"))]
- "(INTVAL (operands[3]) == 0
- || INTVAL (operands[4]) == 0
- || (IN_RANGE_P (INTVAL (operands[3]), -2048, 2047)
- && IN_RANGE_P (INTVAL (operands[4]) - INTVAL (operands[3]), -2048, 2047)))"
- "#"
- [(set_attr "length" "8,12,8,12,12")
- (set_attr "type" "multi")])
-
-(define_insn "*movqicc_internal2_unsigned"
+(define_insn "*movqicc_internal2_int"
[(set (match_operand:QI 0 "integer_register_operand" "=d,d,d,d,d")
- (if_then_else:QI (match_operator:CC_UNS 1 "unsigned_relational_operator"
- [(match_operand:CC_UNS 2 "icc_operand" "t,t,t,t,t")
+ (if_then_else:QI (match_operator 1 "integer_relational_operator"
+ [(match_operand 2 "icc_operand" "t,t,t,t,t")
(const_int 0)])
(match_operand:QI 3 "const_int_operand" "O,O,L,n,n")
(match_operand:QI 4 "const_int_operand" "L,n,O,O,n")))
DONE;
}")
-(define_insn "*movhicc_internal1_signed"
- [(set (match_operand:HI 0 "integer_register_operand" "=d,d,d")
- (if_then_else:HI (match_operator:CC 1 "signed_relational_operator"
- [(match_operand:CC 2 "icc_operand" "t,t,t")
- (const_int 0)])
- (match_operand:HI 3 "reg_or_0_operand" "0,dO,dO")
- (match_operand:HI 4 "reg_or_0_operand" "dO,0,dO")))
- (clobber (match_operand:CC_CCR 5 "icr_operand" "=v,v,v"))]
- ""
- "#"
- [(set_attr "length" "8,8,12")
- (set_attr "type" "multi")])
-
-(define_insn "*movhicc_internal1_unsigned"
+(define_insn "*movhicc_internal1_int"
[(set (match_operand:HI 0 "integer_register_operand" "=d,d,d")
- (if_then_else:HI (match_operator:CC_UNS 1 "unsigned_relational_operator"
- [(match_operand:CC_UNS 2 "icc_operand" "t,t,t")
+ (if_then_else:HI (match_operator 1 "integer_relational_operator"
+ [(match_operand 2 "icc_operand" "t,t,t")
(const_int 0)])
(match_operand:HI 3 "reg_or_0_operand" "0,dO,dO")
(match_operand:HI 4 "reg_or_0_operand" "dO,0,dO")))
[(set_attr "length" "8,8,12")
(set_attr "type" "multi")])
-(define_insn "*movhicc_internal2_signed"
+(define_insn "*movhicc_internal2_int"
[(set (match_operand:HI 0 "integer_register_operand" "=d,d,d,d,d")
- (if_then_else:HI (match_operator:CC 1 "signed_relational_operator"
- [(match_operand:CC 2 "icc_operand" "t,t,t,t,t")
- (const_int 0)])
- (match_operand:HI 3 "const_int_operand" "O,O,L,n,n")
- (match_operand:HI 4 "const_int_operand" "L,n,O,O,n")))
- (clobber (match_operand:CC_CCR 5 "icr_operand" "=v,v,v,v,v"))]
- "(INTVAL (operands[3]) == 0
- || INTVAL (operands[4]) == 0
- || (IN_RANGE_P (INTVAL (operands[3]), -2048, 2047)
- && IN_RANGE_P (INTVAL (operands[4]) - INTVAL (operands[3]), -2048, 2047)))"
- "#"
- [(set_attr "length" "8,12,8,12,12")
- (set_attr "type" "multi")])
-
-(define_insn "*movhicc_internal2_unsigned"
- [(set (match_operand:HI 0 "integer_register_operand" "=d,d,d,d,d")
- (if_then_else:HI (match_operator:CC_UNS 1 "unsigned_relational_operator"
- [(match_operand:CC_UNS 2 "icc_operand" "t,t,t,t,t")
+ (if_then_else:HI (match_operator 1 "integer_relational_operator"
+ [(match_operand 2 "icc_operand" "t,t,t,t,t")
(const_int 0)])
(match_operand:HI 3 "const_int_operand" "O,O,L,n,n")
(match_operand:HI 4 "const_int_operand" "L,n,O,O,n")))
DONE;
}")
-(define_insn "*movsicc_internal1_signed"
- [(set (match_operand:SI 0 "integer_register_operand" "=d,d,d")
- (if_then_else:SI (match_operator:CC 1 "signed_relational_operator"
- [(match_operand:CC 2 "icc_operand" "t,t,t")
- (const_int 0)])
- (match_operand:SI 3 "reg_or_0_operand" "0,dO,dO")
- (match_operand:SI 4 "reg_or_0_operand" "dO,0,dO")))
- (clobber (match_operand:CC_CCR 5 "icr_operand" "=v,v,v"))]
- ""
- "#"
- [(set_attr "length" "8,8,12")
- (set_attr "type" "multi")])
-
-(define_insn "*movsicc_internal1_unsigned"
+(define_insn "*movsicc_internal1_int"
[(set (match_operand:SI 0 "integer_register_operand" "=d,d,d")
- (if_then_else:SI (match_operator:CC_UNS 1 "unsigned_relational_operator"
- [(match_operand:CC_UNS 2 "icc_operand" "t,t,t")
+ (if_then_else:SI (match_operator 1 "integer_relational_operator"
+ [(match_operand 2 "icc_operand" "t,t,t")
(const_int 0)])
(match_operand:SI 3 "reg_or_0_operand" "0,dO,dO")
(match_operand:SI 4 "reg_or_0_operand" "dO,0,dO")))
[(set_attr "length" "8,8,12")
(set_attr "type" "multi")])
-(define_insn "*movsicc_internal2_signed"
- [(set (match_operand:SI 0 "integer_register_operand" "=d,d,d,d,d")
- (if_then_else:SI (match_operator:CC 1 "signed_relational_operator"
- [(match_operand:CC 2 "icc_operand" "t,t,t,t,t")
- (const_int 0)])
- (match_operand:SI 3 "const_int_operand" "O,O,L,n,n")
- (match_operand:SI 4 "const_int_operand" "L,n,O,O,n")))
- (clobber (match_operand:CC_CCR 5 "icr_operand" "=v,v,v,v,v"))]
- "(INTVAL (operands[3]) == 0
- || INTVAL (operands[4]) == 0
- || (IN_RANGE_P (INTVAL (operands[3]), -2048, 2047)
- && IN_RANGE_P (INTVAL (operands[4]) - INTVAL (operands[3]), -2048, 2047)))"
- "#"
- [(set_attr "length" "8,12,8,12,12")
- (set_attr "type" "multi")])
-
-(define_insn "*movsicc_internal2_unsigned"
+(define_insn "*movsicc_internal2_int"
[(set (match_operand:SI 0 "integer_register_operand" "=d,d,d,d,d")
- (if_then_else:SI (match_operator:CC_UNS 1 "unsigned_relational_operator"
- [(match_operand:CC_UNS 2 "icc_operand" "t,t,t,t,t")
+ (if_then_else:SI (match_operator 1 "integer_relational_operator"
+ [(match_operand 2 "icc_operand" "t,t,t,t,t")
(const_int 0)])
(match_operand:SI 3 "const_int_operand" "O,O,L,n,n")
(match_operand:SI 4 "const_int_operand" "L,n,O,O,n")))
DONE;
}")
-(define_insn "*movsfcc_has_fprs_signed"
+(define_insn "*movsfcc_has_fprs_int"
[(set (match_operand:SF 0 "register_operand" "=f,f,f,?f,?f,?d")
- (if_then_else:SF (match_operator:CC 1 "signed_relational_operator"
- [(match_operand:CC 2 "icc_operand" "t,t,t,t,t,t")
- (const_int 0)])
- (match_operand:SF 3 "register_operand" "0,f,f,f,d,fd")
- (match_operand:SF 4 "register_operand" "f,0,f,d,fd,fd")))
- (clobber (match_operand:CC_CCR 5 "icr_operand" "=v,v,v,v,v,v"))]
- "TARGET_HAS_FPRS"
- "#"
- [(set_attr "length" "8,8,12,12,12,12")
- (set_attr "type" "multi")])
-
-(define_insn "*movsfcc_has_fprs_unsigned"
- [(set (match_operand:SF 0 "register_operand" "=f,f,f,?f,?f,?d")
- (if_then_else:SF (match_operator:CC_UNS 1 "unsigned_relational_operator"
- [(match_operand:CC_UNS 2 "icc_operand" "t,t,t,t,t,t")
+ (if_then_else:SF (match_operator 1 "integer_relational_operator"
+ [(match_operand 2 "icc_operand" "t,t,t,t,t,t")
(const_int 0)])
(match_operand:SF 3 "register_operand" "0,f,f,f,d,fd")
(match_operand:SF 4 "register_operand" "f,0,f,d,fd,fd")))
[(set_attr "length" "8,8,12,12,12,12")
(set_attr "type" "multi")])
-(define_insn "*movsfcc_no_fprs_signed"
- [(set (match_operand:SF 0 "integer_register_operand" "=d,d,d")
- (if_then_else:SF (match_operator:CC 1 "signed_relational_operator"
- [(match_operand:CC 2 "icc_operand" "t,t,t")
- (const_int 0)])
- (match_operand:SF 3 "integer_register_operand" "0,d,d")
- (match_operand:SF 4 "integer_register_operand" "d,0,d")))
- (clobber (match_operand:CC_CCR 5 "icr_operand" "=v,v,v"))]
- "! TARGET_HAS_FPRS"
- "#"
- [(set_attr "length" "8,8,12")
- (set_attr "type" "multi")])
-
-(define_insn "*movsfcc_no_fprs_unsigned"
+(define_insn "*movsfcc_no_fprs_int"
[(set (match_operand:SF 0 "integer_register_operand" "=d,d,d")
- (if_then_else:SF (match_operator:CC_UNS 1 "unsigned_relational_operator"
- [(match_operand:CC_UNS 2 "icc_operand" "t,t,t")
+ (if_then_else:SF (match_operator 1 "integer_relational_operator"
+ [(match_operand 2 "icc_operand" "t,t,t")
(const_int 0)])
(match_operand:SF 3 "integer_register_operand" "0,d,d")
(match_operand:SF 4 "integer_register_operand" "d,0,d")))
(define_insn "*return_true"
[(set (pc)
- (if_then_else (match_operator:CC 0 "signed_relational_operator"
- [(match_operand 1 "icc_operand" "t")
- (const_int 0)])
+ (if_then_else (match_operator 0 "integer_relational_operator"
+ [(match_operand 1 "icc_operand" "t")
+ (const_int 0)])
(return)
(pc)))]
"direct_return_p ()"
(define_insn "*return_false"
[(set (pc)
- (if_then_else (match_operator:CC 0 "signed_relational_operator"
- [(match_operand 1 "icc_operand" "t")
- (const_int 0)])
- (pc)
- (return)))]
- "direct_return_p ()"
- "b%C0lr %1,%#"
- [(set_attr "length" "4")
- (set_attr "type" "jump")])
-
-(define_insn "*return_unsigned_true"
- [(set (pc)
- (if_then_else (match_operator:CC_UNS 0 "unsigned_relational_operator"
- [(match_operand 1 "icc_operand" "t")
- (const_int 0)])
- (return)
- (pc)))]
- "direct_return_p ()"
- "b%c0lr %1,%#"
- [(set_attr "length" "4")
- (set_attr "type" "jump")])
-
-(define_insn "*return_unsigned_false"
- [(set (pc)
- (if_then_else (match_operator:CC_UNS 0 "unsigned_relational_operator"
- [(match_operand 1 "icc_operand" "t")
- (const_int 0)])
+ (if_then_else (match_operator 0 "integer_relational_operator"
+ [(match_operand 1 "icc_operand" "t")
+ (const_int 0)])
(pc)
(return)))]
"direct_return_p ()"
projects / gcc.git / commitdiff