Move IntrFlag into the MiscRegFile and get rid of specialized accessor functions.

--HG--
extra : convert_revision : e0d12a150b01d05de9bc02bcbc7c22797975a5b9

diff --git a/src/arch/alpha/isa/decoder.isa b/src/arch/alpha/isa/decoder.isa
index 5bd19b6773cbc003778d329df5299dbc26d8893e..93b941d7295ae167d700fa5d3fe1a2c827106ce5 100644 (file)
--- a/src/arch/alpha/isa/decoder.isa
+++ b/src/arch/alpha/isa/decoder.isa
@@ -661,12 +661,12 @@ decode OPCODE default Unknown::unknown() {
 #if FULL_SYSTEM
         format BasicOperate {
             0xe000: rc({{
-                Ra = xc->readIntrFlag();
-                xc->setIntrFlag(0);
+                Ra = IntrFlag;
+                IntrFlag = 0;
             }}, IsNonSpeculative, IsUnverifiable);
             0xf000: rs({{
-                Ra = xc->readIntrFlag();
-                xc->setIntrFlag(1);
+                Ra = IntrFlag;
+                IntrFlag = 1;
             }}, IsNonSpeculative, IsUnverifiable);
         }
 #else

diff --git a/src/arch/alpha/isa/main.isa b/src/arch/alpha/isa/main.isa
index 2024b1117e3f420e1e30665278ba48d1abdce946..1df6ac60332874fd04f941b22ef522785589bd8c 100644 (file)
--- a/src/arch/alpha/isa/main.isa
+++ b/src/arch/alpha/isa/main.isa
@@ -183,8 +183,9 @@ def operands {{
     'Fc': ('FloatReg', 'df', 'FC', 'IsFloating', 3),
     'Mem': ('Mem', 'uq', None, ('IsMemRef', 'IsLoad', 'IsStore'), 4),
     'NPC': ('NPC', 'uq', None, ( None, None, 'IsControl' ), 4),
-    'Runiq': ('ControlReg', 'uq', 'TheISA::Uniq_DepTag', None, 1),
-    'FPCR':  (' ControlReg', 'uq', 'TheISA::Fpcr_DepTag', None, 1),
+    'Runiq': ('ControlReg', 'uq', 'AlphaISA::Uniq_DepTag', None, 1),
+    'FPCR':  ('ControlReg', 'uq', 'AlphaISA::Fpcr_DepTag', None, 1),
+    'IntrFlag': ('ControlReg', 'uq', 'AlphaISA::Intr_Flag_DepTag', None, 1),
     # The next two are hacks for non-full-system call-pal emulation
     'R0':  ('IntReg', 'uq', '0', None, 1),
     'R16': ('IntReg', 'uq', '16', None, 1),

diff --git a/src/arch/alpha/isa_traits.hh b/src/arch/alpha/isa_traits.hh
index 4f439b8dfe9bba7bf35e6bee5d9f544f2f223028..66cb212356b2ef5477748a3bb6464f5ee9b3d0d3 100644 (file)
--- a/src/arch/alpha/isa_traits.hh
+++ b/src/arch/alpha/isa_traits.hh
@@ -54,7 +54,8 @@ namespace AlphaISA
         Uniq_DepTag = 73,
         Lock_Flag_DepTag = 74,
         Lock_Addr_DepTag = 75,
-        IPR_Base_DepTag = 76
+        Intr_Flag_DepTag = 76,
+        IPR_Base_DepTag = 77
     };
 
     StaticInstPtr decodeInst(ExtMachInst);

diff --git a/src/arch/alpha/regfile.hh b/src/arch/alpha/regfile.hh
index 43b48a0ab2c978dadbf68aaa57ca3ac6352b3aa7..ea6fc67b222c75bc86f35aa8b13b1a567aa3faca 100644 (file)
--- a/src/arch/alpha/regfile.hh
+++ b/src/arch/alpha/regfile.hh
@@ -109,6 +109,7 @@ namespace AlphaISA
         uint64_t       uniq;           // process-unique register
         bool           lock_flag;      // lock flag for LL/SC
         Addr           lock_addr;      // lock address for LL/SC
+        int            intr_flag;
 
       public:
         MiscReg readReg(int misc_reg);
@@ -131,6 +132,7 @@ namespace AlphaISA
             fpcr = uniq = 0;
             lock_flag = 0;
             lock_addr = 0;
+            intr_flag = 0;
         }
 
         void serialize(std::ostream &os);

diff --git a/src/cpu/checker/cpu.hh b/src/cpu/checker/cpu.hh
index 00b01171f46514aa3714eb90adb59b839418cee0..7c01bdc39e9a86770cde5c8b89078ccb5144cfaf 100644 (file)
--- a/src/cpu/checker/cpu.hh
+++ b/src/cpu/checker/cpu.hh
@@ -328,8 +328,6 @@ class CheckerCPU : public BaseCPU
 
 #if FULL_SYSTEM
     Fault hwrei() { return thread->hwrei(); }
-    int readIntrFlag() { return thread->readIntrFlag(); }
-    void setIntrFlag(int val) { thread->setIntrFlag(val); }
     bool inPalMode() { return thread->inPalMode(); }
     void ev5_trap(Fault fault) { fault->invoke(tc); }
     bool simPalCheck(int palFunc) { return thread->simPalCheck(palFunc); }

diff --git a/src/cpu/exec_context.hh b/src/cpu/exec_context.hh
index f6e8d7c2552d7071f0851c2e3811d4fb0a6b929c..e28b33193aac721df394ab2455cd7ce1fd10bffb 100644 (file)
--- a/src/cpu/exec_context.hh
+++ b/src/cpu/exec_context.hh
@@ -144,10 +144,6 @@ class ExecContext {
     /** Somewhat Alpha-specific function that handles returning from
      * an error or interrupt. */
     Fault hwrei();
-    /** Reads the interrupt flags. */
-    int readIntrFlag();
-    /** Sets the interrupt flags to a value. */
-    void setIntrFlag(int val);
 
     /**
      * Check for special simulator handling of specific PAL calls.  If

diff --git a/src/cpu/o3/alpha/cpu.hh b/src/cpu/o3/alpha/cpu.hh
index 9d97f970157d1902208d21c96055c7674f7d2784..474fce02a3fc023874c659f2fd7aca1a09db05f5 100644 (file)
--- a/src/cpu/o3/alpha/cpu.hh
+++ b/src/cpu/o3/alpha/cpu.hh
@@ -145,10 +145,6 @@ class AlphaO3CPU : public FullO3CPU<Impl>
 #if FULL_SYSTEM
     /** Posts an interrupt. */
     void post_interrupt(int int_num, int index);
-    /** Reads the interrupt flag. */
-    int readIntrFlag();
-    /** Sets the interrupt flags. */
-    void setIntrFlag(int val);
     /** HW return from error interrupt. */
     Fault hwrei(unsigned tid);
     /** Returns if a specific PC is a PAL mode PC. */

diff --git a/src/cpu/o3/alpha/cpu_impl.hh b/src/cpu/o3/alpha/cpu_impl.hh
index b7362fad914fc53d371758b59f94fe10cd568b02..a57c5d9ed713968fc3956b73825e4cc8e92b0dc5 100644 (file)
--- a/src/cpu/o3/alpha/cpu_impl.hh
+++ b/src/cpu/o3/alpha/cpu_impl.hh
@@ -241,20 +241,6 @@ AlphaO3CPU<Impl>::post_interrupt(int int_num, int index)
     }
 }
 
-template <class Impl>
-int
-AlphaO3CPU<Impl>::readIntrFlag()
-{
-    return this->regFile.readIntrFlag();
-}
-
-template <class Impl>
-void
-AlphaO3CPU<Impl>::setIntrFlag(int val)
-{
-    this->regFile.setIntrFlag(val);
-}
-
 template <class Impl>
 Fault
 AlphaO3CPU<Impl>::hwrei(unsigned tid)

diff --git a/src/cpu/o3/alpha/dyn_inst_impl.hh b/src/cpu/o3/alpha/dyn_inst_impl.hh
index b273a7b9b732754cbabcdd0f1978070ad9bb0d03..f27cd59614d14b9453c7849dda6cedcfc69e4681 100644 (file)
--- a/src/cpu/o3/alpha/dyn_inst_impl.hh
+++ b/src/cpu/o3/alpha/dyn_inst_impl.hh
@@ -127,20 +127,6 @@ AlphaDynInst<Impl>::hwrei()
     return NoFault;
 }
 
-template <class Impl>
-int
-AlphaDynInst<Impl>::readIntrFlag()
-{
-    return this->cpu->readIntrFlag();
-}
-
-template <class Impl>
-void
-AlphaDynInst<Impl>::setIntrFlag(int val)
-{
-    this->cpu->setIntrFlag(val);
-}
-
 template <class Impl>
 bool
 AlphaDynInst<Impl>::inPalMode()

diff --git a/src/cpu/o3/regfile.hh b/src/cpu/o3/regfile.hh
index 512cf0721c1bc780b9cd30d821832ef4782dd8d1..10f6db390fa70a2d402261b0d980f2eadc183035 100644 (file)
--- a/src/cpu/o3/regfile.hh
+++ b/src/cpu/o3/regfile.hh
@@ -251,12 +251,6 @@ class PhysRegFile
                                                     cpu->tcBase(thread_id));
     }
 
-#if FULL_SYSTEM
-    int readIntrFlag() { return intrflag; }
-    /** Sets an interrupt flag. */
-    void setIntrFlag(int val) { intrflag = val; }
-#endif
-
   public:
     /** (signed) integer register file. */
     IntReg *intRegFile;

diff --git a/src/cpu/ozone/cpu.hh b/src/cpu/ozone/cpu.hh
index 70ec1d101bce1d906e312147fe8be69c454729cc..bd46b198bfc3e43c894a5fc4e94a1bb297a22599 100644 (file)
--- a/src/cpu/ozone/cpu.hh
+++ b/src/cpu/ozone/cpu.hh
@@ -583,8 +583,6 @@ class OzoneCPU : public BaseCPU
 
 #if FULL_SYSTEM
     Fault hwrei();
-    int readIntrFlag() { return thread.intrflag; }
-    void setIntrFlag(int val) { thread.intrflag = val; }
     bool inPalMode() { return AlphaISA::PcPAL(thread.PC); }
     bool inPalMode(Addr pc) { return AlphaISA::PcPAL(pc); }
     bool simPalCheck(int palFunc);

diff --git a/src/cpu/ozone/dyn_inst.hh b/src/cpu/ozone/dyn_inst.hh
index e7390626e16ad6b856b813bd9b951c1585a85105..d3871568a3771b8172f27aba5966861c39830179 100644 (file)
--- a/src/cpu/ozone/dyn_inst.hh
+++ b/src/cpu/ozone/dyn_inst.hh
@@ -238,8 +238,6 @@ class OzoneDynInst : public BaseDynInst<Impl>
 
 #if FULL_SYSTEM
     Fault hwrei();
-    int readIntrFlag();
-    void setIntrFlag(int val);
     bool inPalMode();
     void trap(Fault fault);
     bool simPalCheck(int palFunc);

diff --git a/src/cpu/ozone/dyn_inst_impl.hh b/src/cpu/ozone/dyn_inst_impl.hh
index 9d42ab05b5174f251992e92a33a31dcc5a1cd08f..d86f2dc8b36f716b6599faf9dde68c72feabb791 100644 (file)
--- a/src/cpu/ozone/dyn_inst_impl.hh
+++ b/src/cpu/ozone/dyn_inst_impl.hh
@@ -260,20 +260,6 @@ OzoneDynInst<Impl>::hwrei()
     return NoFault;
 }
 
-template <class Impl>
-int
-OzoneDynInst<Impl>::readIntrFlag()
-{
-return this->cpu->readIntrFlag();
-}
-
-template <class Impl>
-void
-OzoneDynInst<Impl>::setIntrFlag(int val)
-{
-    this->cpu->setIntrFlag(val);
-}
-
 template <class Impl>
 bool
 OzoneDynInst<Impl>::inPalMode()

diff --git a/src/cpu/simple/base.hh b/src/cpu/simple/base.hh
index 1a9fc51270fb802d6d0008fcd668d1ea9b7ac24c..1d208b8df555f4933689c7979b591f225baed328 100644 (file)
--- a/src/cpu/simple/base.hh
+++ b/src/cpu/simple/base.hh
@@ -305,8 +305,6 @@ class BaseSimpleCPU : public BaseCPU
 
 #if FULL_SYSTEM
     Fault hwrei() { return thread->hwrei(); }
-    int readIntrFlag() { return thread->readIntrFlag(); }
-    void setIntrFlag(int val) { thread->setIntrFlag(val); }
     bool inPalMode() { return thread->inPalMode(); }
     void ev5_trap(Fault fault) { fault->invoke(tc); }
     bool simPalCheck(int palFunc) { return thread->simPalCheck(palFunc); }

diff --git a/src/cpu/simple_thread.hh b/src/cpu/simple_thread.hh
index 10ec8faaaf2fd08971aef1d0cadd4f72bb42e77c..d005b2914f2fe14a81b1982741486cbe0e1c3b98 100644 (file)
--- a/src/cpu/simple_thread.hh
+++ b/src/cpu/simple_thread.hh
@@ -168,8 +168,6 @@ class SimpleThread : public ThreadState
 
     void dumpFuncProfile();
 
-    int readIntrFlag() { return regs.intrflag; }
-    void setIntrFlag(int val) { regs.intrflag = val; }
     Fault hwrei();
 
     bool simPalCheck(int palFunc);