+2015-09-08 Alan Lawrence <alan.lawrence@arm.com>
+
+ * config/aarch64/aarch64-simd.md (aarch64_simd_vec_unpacks_lo_<mode>,
+ aarch64_simd_vec_unpacks_hi_<mode>): New insn.
+ (vec_unpacks_lo_v4sf, vec_unpacks_hi_v4sf): Delete insn.
+ (vec_unpacks_lo_<mode>, vec_unpacks_hi_<mode>): New expand.
+ (aarch64_float_extend_lo_v2df): Rename to...
+ (aarch64_float_extend_lo_<Vwide>): this, using VDF and so adding V4SF.
+
+ * config/aarch64/aarch64-simd-builtins.def (vec_unpacks_hi): Add v8hf.
+ (float_extend_lo): Add v4sf.
+
+ * config/aarch64/arm_neon.h (vcvt_f32_f16, vcvt_high_f32_f16): New.
+ * config/aarch64/iterators.md (VQ_HSF): New iterator.
+ (VWIDE, Vwtype, Vhalftype): Add V8HF, V4SF.
+ (Vwide): New mode_attr.
+
2015-09-08 Alan Lawrence <alan.lawrence@arm.com>
* config/aarch64/aarch64-simd.md (aarch64_simd_dup<mode>,
BUILTIN_VSDQ_I_DI (UNOP, abs, 0)
BUILTIN_VDQF (UNOP, abs, 2)
- VAR1 (UNOP, vec_unpacks_hi_, 10, v4sf)
+ BUILTIN_VQ_HSF (UNOP, vec_unpacks_hi_, 10)
VAR1 (BINOP, float_truncate_hi_, 0, v4sf)
VAR1 (BINOP, float_truncate_hi_, 0, v8hf)
VAR1 (UNOP, float_extend_lo_, 0, v2df)
+ VAR1 (UNOP, float_extend_lo_, 0, v4sf)
BUILTIN_VDF (UNOP, float_truncate_lo_, 0)
/* Implemented by aarch64_ld1<VALL_F16:mode>. */
;; Float widening operations.
-(define_insn "vec_unpacks_lo_v4sf"
- [(set (match_operand:V2DF 0 "register_operand" "=w")
- (float_extend:V2DF
- (vec_select:V2SF
- (match_operand:V4SF 1 "register_operand" "w")
- (parallel [(const_int 0) (const_int 1)])
- )))]
+(define_insn "aarch64_simd_vec_unpacks_lo_<mode>"
+ [(set (match_operand:<VWIDE> 0 "register_operand" "=w")
+ (float_extend:<VWIDE> (vec_select:<VHALF>
+ (match_operand:VQ_HSF 1 "register_operand" "w")
+ (match_operand:VQ_HSF 2 "vect_par_cnst_lo_half" "")
+ )))]
"TARGET_SIMD"
- "fcvtl\\t%0.2d, %1.2s"
+ "fcvtl\\t%0.<Vwtype>, %1.<Vhalftype>"
[(set_attr "type" "neon_fp_cvt_widen_s")]
)
-(define_insn "aarch64_float_extend_lo_v2df"
- [(set (match_operand:V2DF 0 "register_operand" "=w")
- (float_extend:V2DF
- (match_operand:V2SF 1 "register_operand" "w")))]
+(define_expand "vec_unpacks_lo_<mode>"
+ [(match_operand:<VWIDE> 0 "register_operand" "")
+ (match_operand:VQ_HSF 1 "register_operand" "")]
"TARGET_SIMD"
- "fcvtl\\t%0.2d, %1.2s"
+ {
+ rtx p = aarch64_simd_vect_par_cnst_half (<MODE>mode, false);
+ emit_insn (gen_aarch64_simd_vec_unpacks_lo_<mode> (operands[0],
+ operands[1], p));
+ DONE;
+ }
+)
+
+(define_insn "aarch64_simd_vec_unpacks_hi_<mode>"
+ [(set (match_operand:<VWIDE> 0 "register_operand" "=w")
+ (float_extend:<VWIDE> (vec_select:<VHALF>
+ (match_operand:VQ_HSF 1 "register_operand" "w")
+ (match_operand:VQ_HSF 2 "vect_par_cnst_hi_half" "")
+ )))]
+ "TARGET_SIMD"
+ "fcvtl2\\t%0.<Vwtype>, %1.<Vtype>"
[(set_attr "type" "neon_fp_cvt_widen_s")]
)
-(define_insn "vec_unpacks_hi_v4sf"
- [(set (match_operand:V2DF 0 "register_operand" "=w")
- (float_extend:V2DF
- (vec_select:V2SF
- (match_operand:V4SF 1 "register_operand" "w")
- (parallel [(const_int 2) (const_int 3)])
- )))]
+(define_expand "vec_unpacks_hi_<mode>"
+ [(match_operand:<VWIDE> 0 "register_operand" "")
+ (match_operand:VQ_HSF 1 "register_operand" "")]
+ "TARGET_SIMD"
+ {
+ rtx p = aarch64_simd_vect_par_cnst_half (<MODE>mode, true);
+ emit_insn (gen_aarch64_simd_vec_unpacks_lo_<mode> (operands[0],
+ operands[1], p));
+ DONE;
+ }
+)
+(define_insn "aarch64_float_extend_lo_<Vwide>"
+ [(set (match_operand:<VWIDE> 0 "register_operand" "=w")
+ (float_extend:<VWIDE>
+ (match_operand:VDF 1 "register_operand" "w")))]
"TARGET_SIMD"
- "fcvtl2\\t%0.2d, %1.4s"
+ "fcvtl\\t%0<Vmwtype>, %1<Vmtype>"
[(set_attr "type" "neon_fp_cvt_widen_s")]
)
result; \
})
-/* vcvt_f32_f16 not supported */
-
-/* vcvt_high_f32_f16 not supported */
-
#define vcvt_n_f32_s32(a, b) \
__extension__ \
({ \
/* vcvt (float -> double). */
+__extension__ static __inline float32x4_t __attribute__ ((__always_inline__))
+vcvt_f32_f16 (float16x4_t __a)
+{
+ return __builtin_aarch64_float_extend_lo_v4sf (__a);
+}
+
__extension__ static __inline float64x2_t __attribute__ ((__always_inline__))
vcvt_f64_f32 (float32x2_t __a)
{
return __builtin_aarch64_float_extend_lo_v2df (__a);
}
+__extension__ static __inline float32x4_t __attribute__ ((__always_inline__))
+vcvt_high_f32_f16 (float16x8_t __a)
+{
+ return __builtin_aarch64_vec_unpacks_hi_v8hf (__a);
+}
+
__extension__ static __inline float64x2_t __attribute__ ((__always_inline__))
vcvt_high_f64_f32 (float32x4_t __a)
{
;; Vector single Float modes.
(define_mode_iterator VDQSF [V2SF V4SF])
+;; Quad vector Float modes with half/single elements.
+(define_mode_iterator VQ_HSF [V8HF V4SF])
+
;; Modes suitable to use as the return type of a vcond expression.
(define_mode_iterator VDQF_COND [V2SF V2SI V4SF V4SI V2DF V2DI])
(V2SI "V2DI") (V16QI "V8HI")
(V8HI "V4SI") (V4SI "V2DI")
(HI "SI") (SI "DI")
+ (V8HF "V4SF") (V4SF "V2DF")
(V4HF "V4SF") (V2SF "V2DF")]
-
)
-;; Widened mode register suffixes for VD_BHSI/VQW.
+;; Widened modes of vector modes, lowercase
+(define_mode_attr Vwide [(V2SF "v2df") (V4HF "v4sf")])
+
+;; Widened mode register suffixes for VD_BHSI/VQW/VQ_HSF.
(define_mode_attr Vwtype [(V8QI "8h") (V4HI "4s")
(V2SI "2d") (V16QI "8h")
- (V8HI "4s") (V4SI "2d")])
+ (V8HI "4s") (V4SI "2d")
+ (V8HF "4s") (V4SF "2d")])
;; Widened mode register suffixes for VDW/VQW.
(define_mode_attr Vmwtype [(V8QI ".8h") (V4HI ".4s")
(V4HF ".4s") (V2SF ".2d")
(SI "") (HI "")])
-;; Lower part register suffixes for VQW.
+;; Lower part register suffixes for VQW/VQ_HSF.
(define_mode_attr Vhalftype [(V16QI "8b") (V8HI "4h")
- (V4SI "2s")])
+ (V4SI "2s") (V8HF "4h")
+ (V4SF "2s")])
;; Define corresponding core/FP element mode for each vector mode.
(define_mode_attr vw [(V8QI "w") (V16QI "w")
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