bank/csrgen: interface -> bus

diff --git a/top.py b/top.py
index 33708a9f6a140cb7429e4314ae3d8a558480c2a1..419ee9d0fd08a17b20529e31936a59d456667ee1 100644 (file)
--- a/top.py
+++ b/top.py
@@ -114,13 +114,13 @@ def get():
        fb0 = framebuffer.Framebuffer(csr_offset("FB"), asmiport_fb)
        asmiprobe0 = asmiprobe.ASMIprobe(csr_offset("ASMIPROBE"), asmicon0.hub)
        csrcon0 = csr.Interconnect(wishbone2csr0.csr, [
-               uart0.bank.interface,
-               dfii0.bank.interface,
-               identifier0.bank.interface,
-               timer0.bank.interface,
-               minimac0.bank.interface,
-               fb0.bank.interface,
-               asmiprobe0.bank.interface
+               uart0.bank.bus,
+               dfii0.bank.bus,
+               identifier0.bank.bus,
+               timer0.bank.bus,
+               minimac0.bank.bus,
+               fb0.bank.bus,
+               asmiprobe0.bank.bus
        ])
        
        #