Merge zeep.pool:/z/saidi/work/m5.head

into  zeep.pool:/z/saidi/work/m5.nm_m5_pull

SConscript:
    dram memory needs to be converted to newmem before we can use it
dev/ide_ctrl.cc:
    don't need this printing in newmem
dev/ide_disk.cc:
    will read stats in next commit
dev/sinic.cc:
    merge sinic from head, still needs work

--HG--
extra : convert_revision : b9aabd8c7814d07d54ce6f971aad3ec349fa24e1

diff --cc arch/alpha/isa/decoder.isa
Simple merge

diff --cc dev/ide_disk.hh
Simple merge

diff --cc dev/sinic.cc
index b5b6c6cf551db9516a255e05f9ae4f2590677d48,0853717bacd74ccf31481d5a9bc602436db0698b..66ca88dbe757f1f12984efb51e434c3f733aeb67
--- 1/dev/sinic.cc
--- 2/dev/sinic.cc
+++ b/dev/sinic.cc
@@@ -81,7 -85,9 +81,8 @@@ Base::Base(Params *p
  }
  
  Device::Device(Params *p)
-     : Base(p), rxFifo(p->rx_fifo_size), txFifo(p->tx_fifo_size),
+     : Base(p), plat(p->plat), physmem(p->physmem), rxUnique(0), txUnique(0),
+       virtualRegs(p->virtual_count < 1 ? 1 : p->virtual_count),
 -      rxFifo(p->rx_fifo_size), txFifo(p->tx_fifo_size),
        rxKickTick(0), txKickTick(0),
        txEvent(this), rxDmaEvent(this), txDmaEvent(this),
        dmaReadDelay(p->dma_read_delay), dmaReadFactor(p->dma_read_factor),
@@@ -321,21 -381,20 +322,22 @@@ Device::read(Packet &pkt
      Addr index = daddr >> Regs::VirtualShift;
      Addr raddr = daddr & Regs::VirtualMask;
  
 +    pkt.time += pioDelay;
 +    pkt.allocate();
 +
      if (!regValid(raddr))
-         panic("invalid register: cpu=%d, da=%#x pa=%#x size=%d",
-                 cpu, daddr, pkt.addr, pkt.size);
 -        panic("invalid register: cpu=%d vnic=%d da=%#x pa=%#x va=%#x size=%d",
 -              cpu, index, daddr, req->paddr, req->vaddr, req->size);
++        panic("invalid register: cpu=%d vnic=%d da=%#x pa=%#x size=%d",
++              cpu, index, daddr, pkt.addr, pkt.size);
  
      const Regs::Info &info = regInfo(raddr);
      if (!info.read)
-         panic("reading %s (write only): cpu=%d da=%#x pa=%#x size=%d",
-                 info.name, cpu, daddr, pkt.addr, pkt.size);
+         panic("read %s (write only): "
 -              "cpu=%d vnic=%d da=%#x pa=%#x va=%#x size=%d",
 -              info.name, cpu, index, daddr, req->paddr, req->vaddr, req->size);
++              "cpu=%d vnic=%d da=%#x pa=%#x size=%d",
++              info.name, cpu, index, daddr, pkt.addr, pkt.size);
  
-     if (pkt.size != info.size)
-         panic("invalid size for reg %s: cpu=%d da=%#x pa=%#x size=%d",
-                 info.name, cpu, daddr, pkt.addr, pkt.size);
 -    if (req->size != info.size)
+         panic("read %s (invalid size): "
 -              "cpu=%d vnic=%d da=%#x pa=%#x va=%#x size=%d",
 -              info.name, cpu, index, daddr, req->paddr, req->vaddr, req->size);
++              "cpu=%d vnic=%d da=%#x pa=%#x size=%d",
++              info.name, cpu, index, daddr, pkt.addr, pkt.size);
  
      prepareRead(cpu, index);
  
@@@ -353,8 -412,9 +355,8 @@@
      }
  
      DPRINTF(EthernetPIO,
-             "read %s cpu=%d da=%#x pa=%#x size=%d val=%#x\n",
-             info.name, cpu, daddr, pkt.addr, pkt.size, value);
 -            "read %s: cpu=%d vnic=%d da=%#x pa=%#x va=%#x size=%d val=%#x\n",
 -            info.name, cpu, index, daddr, req->paddr, req->vaddr, req->size,
 -            value);
++            "read %s: cpu=%d vnic=%d da=%#x pa=%#x size=%d val=%#x\n",
++            info.name, cpu, index, daddr, pkt.addr, pkt.size, value);
  
      // reading the interrupt status register has the side effect of
      // clearing it
@@@ -416,19 -486,23 +418,21 @@@ Device::write(Packet &pkt
  
      const Regs::Info &info = regInfo(raddr);
      if (!info.write)
-         panic("write %s (read only): cpu=%d da=%#x pa=%#x size=%d",
-                 info.name, cpu, daddr, pkt.addr, pkt.size);
+         panic("write %s (read only): "
 -              "cpu=%d vnic=%d da=%#x pa=%#x va=%#x size=%d",
 -              info.name, cpu, index, daddr, req->paddr, req->vaddr, req->size);
++              "cpu=%d vnic=%d da=%#x pa=%#x size=%d",
++              info.name, cpu, index, daddr, pkt.addr, pkt.size);
  
 -    if (req->size != info.size)
 +    if (pkt.size != info.size)
-         panic("invalid size for reg %s: cpu=%d da=%#x pa=%#x size=%d",
-                 info.name, cpu, daddr, pkt.addr, pkt.size);
+         panic("write %s (invalid size): "
 -              "cpu=%d vnic=%d da=%#x pa=%#x va=%#x size=%d",
 -              info.name, cpu, index, daddr, req->paddr, req->vaddr, req->size);
++              "cpu=%d vnic=%d da=%#x pa=%#x size=%d",
++              info.name, cpu, index, daddr, pkt.addr, pkt.size);
  
 -    uint32_t reg32 = *(uint32_t *)data;
 -    uint64_t reg64 = *(uint64_t *)data;
      VirtualReg &vnic = virtualRegs[index];
  
      DPRINTF(EthernetPIO,
-             "write %s: cpu=%d val=%#x da=%#x pa=%#x size=%d\n",
-             info.name, cpu, info.size == 4 ? pkt.get<uint32_t>() :
 -            "write %s vnic %d: cpu=%d val=%#x da=%#x pa=%#x va=%#x size=%d\n",
 -            info.name, index, cpu, info.size == 4 ? reg32 : reg64, daddr,
 -            req->paddr, req->vaddr, req->size);
++            "write %s vnic %d: cpu=%d val=%#x da=%#x pa=%#x size=%d\n",
++            info.name, index, cpu, info.size == 4 ? pkt.get<uint32_t>() :
 +            pkt.get<uint64_t>(), daddr, pkt.addr, pkt.size);
  
      prepareWrite(cpu, index);
  
@@@ -454,10 -528,32 +458,32 @@@
              panic("receive machine busy with another request! rxState=%s",
                    RxStateStrings[rxState]);
  
+         vnic.rxUnique = rxUnique++;
          vnic.RxDone = Regs::RxDone_Busy;
 -        vnic.RxData = reg64;
 +        vnic.RxData = pkt.get<uint64_t>();
-         rxList.push_back(index);
-         if (rxEnable && rxState == rxIdle) {
+ 
+         if (Regs::get_RxData_Vaddr(reg64)) {
+             Addr vaddr = Regs::get_RxData_Addr(reg64);
+             Addr paddr = vtophys(req->xc, vaddr);
+             DPRINTF(EthernetPIO, "write RxData vnic %d (rxunique %d): "
+                     "vaddr=%#x, paddr=%#x\n",
+                     index, vnic.rxUnique, vaddr, paddr);
+ 
+             vnic.RxData = Regs::set_RxData_Addr(vnic.RxData, paddr);
+         } else {
+             DPRINTF(EthernetPIO, "write RxData vnic %d (rxunique %d)\n",
+                     index, vnic.rxUnique);
+         }
+ 
+         if (vnic.rxPacket == rxFifo.end()) {
+             DPRINTF(EthernetPIO, "request new packet...appending to rxList\n");
+             rxList.push_back(index);
+         } else {
+             DPRINTF(EthernetPIO, "packet exists...appending to rxBusy\n");
+             rxBusy.push_back(index);
+         }
+ 
+         if (rxEnable && (rxState == rxIdle || rxState == rxFifoBlock)) {
              rxState = rxFifoBlock;
              rxKick();
          }
@@@ -468,8 -564,23 +494,23 @@@
              panic("transmit machine busy with another request! txState=%s",
                    TxStateStrings[txState]);
  
+         vnic.txUnique = txUnique++;
          vnic.TxDone = Regs::TxDone_Busy;
-         vnic.TxData = pkt.get<uint64_t>();
 -        vnic.TxData = reg64;
+ 
 -        if (Regs::get_TxData_Vaddr(reg64)) {
 -            Addr vaddr = Regs::get_TxData_Addr(reg64);
++        if (Regs::get_TxData_Vaddr(pkt.get<uint64_t>())) {
++            panic("vtophys won't work here in newmem.\n");
++            /*Addr vaddr = Regs::get_TxData_Addr(reg64);
+             Addr paddr = vtophys(req->xc, vaddr);
+             DPRINTF(EthernetPIO, "write TxData vnic %d (rxunique %d): "
+                     "vaddr=%#x, paddr=%#x\n",
+                     index, vnic.txUnique, vaddr, paddr);
+ 
 -            vnic.TxData = Regs::set_TxData_Addr(vnic.TxData, paddr);
++            vnic.TxData = Regs::set_TxData_Addr(vnic.TxData, paddr);*/
+         } else {
+             DPRINTF(EthernetPIO, "write TxData vnic %d (rxunique %d)\n",
+                     index, vnic.txUnique);
+         }
+ 
          if (txList.empty() || txList.front() != index)
              txList.push_back(index);
          if (txEnable && txState == txIdle && txList.front() == index) {
@@@ -729,9 -854,18 +784,9 @@@ Device::rxDmaDone(
  {
      assert(rxState == rxCopy);
      rxState = rxCopyDone;
-     DPRINTF(EthernetDMA, "rx dma write paddr=%#x len=%d\n",
 -    DPRINTF(EthernetDMA, "begin rx dma write paddr=%#x len=%d\n",
 -            rxDmaAddr, rxDmaLen);
 -    physmem->dma_write(rxDmaAddr, (uint8_t *)rxDmaData, rxDmaLen);
+     DPRINTF(EthernetDMA, "end rx dma write paddr=%#x len=%d\n",
              rxDmaAddr, rxDmaLen);
      DDUMP(EthernetData, rxDmaData, rxDmaLen);
 -}
 -
 -void
 -Device::rxDmaDone()
 -{
 -    rxDmaCopy();
  
      // If the transmit state machine  has a pending DMA, let it go first
      if (txState == txBeginCopy)
@@@ -826,8 -1009,26 +931,13 @@@ Device::rxKick(
                              vnic->rxPacketBytes);
          rxDmaData = (*vnic->rxPacket)->data + vnic->rxPacketOffset;
          rxState = rxCopy;
 -
+         if (rxDmaAddr == 1LL) {
+             rxState = rxCopyDone;
+             break;
+         }
+ 
 -        if (dmaInterface) {
 -            dmaInterface->doDMA(WriteInvalidate, rxDmaAddr, rxDmaLen,
 -                                curTick, &rxDmaEvent, true);
 -            goto exit;
 -        }
 -
 -        if (dmaWriteDelay != 0 || dmaWriteFactor != 0) {
 -            Tick factor = ((rxDmaLen + ULL(63)) >> ULL(6)) * dmaWriteFactor;
 -            Tick start = curTick + dmaWriteDelay + factor;
 -            rxDmaEvent.schedule(start);
 -            goto exit;
 -        }
  
 -        rxDmaCopy();
 +        dmaWrite(rxDmaAddr, rxDmaLen, &rxDmaEvent, rxDmaData);
          break;
  
        case rxCopy:
@@@ -968,10 -1191,10 +1093,10 @@@ Device::txKick(
  
      switch (txState) {
        case txFifoBlock:
-         assert(Regs::get_TxDone_Busy(vnic->TxData));
+         assert(Regs::get_TxDone_Busy(vnic->TxDone));
          if (!txPacket) {
              // Grab a new packet from the fifo.
 -            txPacket = new PacketData(16384);
 +            txPacket = new EthPacketData(16384);
              txPacketOffset = 0;
          }
  
@@@ -1211,8 -1446,10 +1336,10 @@@ Base::unserialize(Checkpoint *cp, cons
  }
  
  void
 -Device::serialize(ostream &os)
 +Device::serialize(std::ostream &os)
  {
+     int count;
+ 
      // Serialize the PciDev base class
      Base::serialize(os);
  

diff --cc dev/sinic.hh
Simple merge

diff --cc python/m5/objects/Ethernet.py
Simple merge