Fixed missing image, clarified IOMux, pinmux signals

diff --git a/docs/pinmux.mdwn b/docs/pinmux.mdwn
index a3b953c8cafa8b8e5b77901f880645324f9381d9..46388545a4aa9f93d5fdcf2f3912b9a98cc24abe 100644 (file)
--- a/docs/pinmux.mdwn
+++ b/docs/pinmux.mdwn
@@ -423,8 +423,6 @@ The following diagram is an example of a GPIO block with switchable banks and co
 
 ## Our Pinmux Block
 
-[[!img banked_gpio_block.jpg size="600x"]]
-
 The block we are developing is very similar, but is lacking some of
 configuration of the former (due to complexity and time constraints).
 
@@ -479,7 +477,7 @@ For example, if 16 GPIOs are instantiated and 64-bit data bus is used, GPIOs
 
 ### Example Memory Map
 
-[[!img gpio-memory-layout.jpg size="600x"]]
+[[!img gpio-mem-layout.jpg size="600x"]]
 
 The diagrams above show the difference in memory layout between 16-GPIO block
 implemented with 64-bit and 32-bit WB data buses.
@@ -534,13 +532,13 @@ because these should be equal.
 
 [[!img iomux-4bank.svg size="600x"]]
 
-This block is an N-to-1 mux and it simultaneously connects:
+This block is an N-to-1 (4 bank shown above) mux and it simultaneously connects:
 
 * o/oe signals from one of N peripheral ports, to the pad output port
 
 * i pad port signal to one of N peripheral ports (the rest being set to 0).
 
-*(NOTE: an N-pin 4-port IOMux has not been implemented yet - do it within the pinmux instead?)*
+*(NOTE: an N-pin 4-bank IOMux has not been implemented yet - do it within the pinmux instead?)*
 
 ## Combined Block
 
@@ -590,14 +588,14 @@ still connected to the GPIO block (via the BS chain).
 
 Signals for various ports:
 
-* WB bus or Periph0: WB data read, data write, address, cyc, stb, ack
-* Periph1/2/3: o,oe,i,ie (puen/pden are only controlled by WB, test port, or
-fixed by functionality)
-* Test port: bank_select[2:0], o,oe,i,ie,puen,pden. In addition, internal
+* WB bus or Periph0: WB data read, data write, address, sel, cyc, stb, ack
+* Periph1/2/3: o,oe,i (puen/pden are only controlled by WB, test port, or
+fixed by functionality; ie not used yet)
+* (?) Test port: bank[2:0], o,oe,i,ie,puen,pden. In addition, internal
 address to access individual GPIOs will be available (this will consist of a
 few bits, as more than 16 GPIOs per block is likely to be to big).
 
-As you can see by the above list, the GPIO block is becoming quite a complex
+As you can see by the above list, the pinmux block is becoming quite a complex
 beast. If there are suggestions to simplify or reduce some of the signals,
 that will be helpful.