RISC-V: Fix assembler for c.addi, rd can be x0

opcodes/ChangeLog:

2017-03-14  Kito Cheng  <kito.cheng@gmail.com>

	* riscv-opc.c (riscv_opcodes) <c.addi>: Use match_opcode.

diff --git a/opcodes/ChangeLog b/opcodes/ChangeLog
index 622ccf49c686af97b8b4820948e253d6909ac895..d4730740ffee206330d06acaedde1f15823d5738 100644 (file)
--- a/opcodes/ChangeLog
+++ b/opcodes/ChangeLog
@@ -1,3 +1,7 @@
+2017-03-14  Kito Cheng  <kito.cheng@gmail.com>
+
+       * riscv-opc.c (riscv_opcodes) <c.addi>: Use match_opcode.
+
 2017-03-13  Andrew Waterman  <andrew@sifive.com>
 
        * riscv-opc.c (riscv_opcodes) <srli/C>: Use match_opcode.

diff --git a/opcodes/riscv-opc.c b/opcodes/riscv-opc.c
index 1bb90ee13ea90005bbc95ee2f7052edea5f73164..4a2ab7b455c1595e233c115599aa0243e5d1134d 100644 (file)
--- a/opcodes/riscv-opc.c
+++ b/opcodes/riscv-opc.c
@@ -625,7 +625,7 @@ const struct riscv_opcode riscv_opcodes[] =
 {"c.li",      "C",   "d,Cj",  MATCH_C_LI, MASK_C_LI, match_rd_nonzero, 0 },
 {"c.addi4spn","C",   "Ct,Cc,CK", MATCH_C_ADDI4SPN, MASK_C_ADDI4SPN, match_opcode, 0 },
 {"c.addi16sp","C",   "Cc,CL", MATCH_C_ADDI16SP, MASK_C_ADDI16SP, match_opcode, 0 },
-{"c.addi",    "C",   "d,Cj",  MATCH_C_ADDI, MASK_C_ADDI, match_rd_nonzero, 0 },
+{"c.addi",    "C",   "d,Cj",  MATCH_C_ADDI, MASK_C_ADDI, match_opcode, 0 },
 {"c.add",     "C",   "d,CV",  MATCH_C_ADD, MASK_C_ADD, match_c_add, 0 },
 {"c.sub",     "C",   "Cs,Ct",  MATCH_C_SUB, MASK_C_SUB, match_opcode, 0 },
 {"c.and",     "C",   "Cs,Ct",  MATCH_C_AND, MASK_C_AND, match_opcode, 0 },