/util/term/m5term
/system/arm/dt/*.dtb
/system/arm/dt/.gen
-/system/arm/simple_bootloader/*.o
-/system/arm/simple_bootloader/boot.arm
-/system/arm/simple_bootloader/boot_emm.arm
-/system/arm/aarch64_bootloader/*.o
-/system/arm/aarch64_bootloader/boot.arm64
-/system/arm/aarch64_bootloader/boot_emm.arm64
-/system/arm/aarch64_bootloader/boot_v2.arm64
+/system/arm/bootloader/arm/*.o
+/system/arm/bootloader/arm/boot.arm
+/system/arm/bootloader/arm/boot_emm.arm
+/system/arm/bootloader/arm64/*.o
+/system/arm/bootloader/arm64/boot.arm64
+/system/arm/bootloader/arm64/boot_emm.arm64
+/system/arm/bootloader/arm64/boot_v2.arm64
+++ /dev/null
-/*
- * Copyright (c) 2012 ARM Limited
- * All rights reserved
- *
- * The license below extends only to copyright in the software and shall
- * not be construed as granting a license to any other intellectual
- * property including but not limited to intellectual property relating
- * to a hardware implementation of the functionality of the software
- * licensed hereunder. You may use the software subject to the license
- * terms below provided that you ensure that this notice is replicated
- * unmodified and in its entirety in all distributions of the software,
- * modified or unmodified, in source code or in binary form.
- *
- * Redistribution and use in source and binary forms, with or without
- * modification, are permitted provided that the following conditions are
- * met: redistributions of source code must retain the above copyright
- * notice, this list of conditions and the following disclaimer;
- * redistributions in binary form must reproduce the above copyright
- * notice, this list of conditions and the following disclaimer in the
- * documentation and/or other materials provided with the distribution;
- * neither the name of the copyright holders nor the names of its
- * contributors may be used to endorse or promote products derived from
- * this software without specific prior written permission.
- *
- * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
- * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
- * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
- * A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT
- * OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,
- * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
- * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
- * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
- * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
- * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
- * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
- *
- */
-
- .text
-
- .globl _start
-_start:
- /*
- * EL3 initialisation
- */
- mrs x0, CurrentEL
- cmp x0, #0xc // EL3?
- b.ne start_ns // skip EL3 initialisation
-
- mov x0, #0x30 // RES1
- orr x0, x0, #(1 << 0) // Non-secure EL1
- orr x0, x0, #(1 << 8) // HVC enable
- orr x0, x0, #(1 << 10) // 64-bit EL2
- msr scr_el3, x0
-
- msr cptr_el3, xzr // Disable copro. traps to EL3
-
- ldr x0, =CNTFRQ
- msr cntfrq_el0, x0
-
- /*
- * Check for the primary CPU to avoid a race on the distributor
- * registers.
- */
- mrs x0, mpidr_el1
- // ARM MPIDR_EL1 bytes: Aff3 (AArch64), Stuff, Aff2, Aff1, Aff0
- // Test the the MPIDR_EL1 register against 0xff00ffffff to
- // extract the primary CPU.
- ldr x1, =0xff00ffffff
-#ifdef GICV3
- and x2, x0, #0xff // use Aff0 as cpuid for now...
- tst x0, x1 // check for cpuid==zero
- b.ne 1f // secondary CPU
-
- ldr x1, =GIC_DIST_BASE // GICD_CTLR
- mov w0, #7 // EnableGrp0 | EnableGrp1NS | EnableGrp1S
- str w0, [x1]
-
-
-1: ldr x1, =GIC_REDIST_BASE + 0x10000 + 0x80 // GICR_IGROUPR0
- // 128K for each redistributor, 256K strided...
- mov x3, #1 << 18 // GICv4
- mul x3, x3, x2
- add x1, x1, x3
- mov w0, #~0 // Grp1 interrupts
- str w0, [x1], #4
- b.ne 2f // Only local interrupts for secondary CPUs
- ldr x1, =GIC_DIST_BASE + 0x84 // GICD_IGROUPR
- str w0, [x1], #4
- str w0, [x1], #4
- str w0, [x1], #4
-
- /* SRE & Disable IRQ/FIQ Bypass & Allow EL2 access to ICC_SRE_EL2 */
-2: mrs x10, S3_6_C12_C12_5 // read ICC_SRE_EL3
- orr x10, x10, #0xf // enable 0xf
- msr S3_6_C12_C12_5, x10 // write ICC_SRE_EL3
- isb
-
- mov x0, #1
- msr S3_0_c12_c12_6, x0 // ICC_IGRPEN0_EL1 Enable
- msr S3_0_C12_C12_7, x0 // ICC_IGRPEN1_EL1 Enable
-#else
- tst x0, x1 // check for cpuid==zero
- b.ne 1f // secondary CPU
-
- ldr x1, =GIC_DIST_BASE // GICD_CTLR
- mov w0, #3 // EnableGrp0 | EnableGrp1
- str w0, [x1]
-
-1: ldr x1, =GIC_DIST_BASE + 0x80 // GICD_IGROUPR
- mov w0, #~0 // Grp1 interrupts
- str w0, [x1], #4
- b.ne 2f // Only local interrupts for secondary CPUs
- str w0, [x1], #4
- str w0, [x1], #4
-
-2: ldr x1, =GIC_CPU_BASE // GICC_CTLR
- ldr w0, [x1]
- mov w0, #3 // EnableGrp0 | EnableGrp1
- str w0, [x1]
-
- mov w0, #1 << 7 // allow NS access to GICC_PMR
- str w0, [x1, #4] // GICC_PMR
-#endif
-
- msr sctlr_el2, xzr
-
- /*
- * Prepare the switch to the EL2_SP1 mode from EL3
- */
- ldr x0, =start_ns // Return after mode switch
- mov x1, #0x3c9 // EL2_SP1 | D | A | I | F
- msr elr_el3, x0
- msr spsr_el3, x1
- eret
-
-start_ns:
- /*
- * Kernel parameters
- */
- mov x0, xzr
- mov x1, xzr
- mov x2, xzr
- mov x3, xzr
-
- mrs x4, mpidr_el1
- // ARM MPIDR_EL1 bytes: Aff3 (AArch64), Stuff, Aff2, Aff1, Aff0
- // Test the the MPIDR_EL1 register against 0xff00ffffff to
- // extract the primary CPU.
- ldr x1, =0xff00ffffff
- tst x4, x1 // check for cpuid==zero
- mov x1, xzr // load previous 'xzr' value back to x1
- b.eq 2f // secondary CPU
-
- /*
- * Secondary CPUs
- */
-1: wfe
- ldr x4, =PHYS_OFFSET + 0xfff8
- ldr x4, [x4]
- cbz x4, 1b
- br x4 // branch to the given address
-
-2:
- /*
- * UART initialisation (38400 8N1)
- */
- ldr x4, =UART_BASE // UART base
- mov w5, #0x10 // ibrd
- str w5, [x4, #0x24]
- mov w5, #0xc300
- orr w5, w5, #0x0001 // cr
- str w5, [x4, #0x30]
-
- /*
- * CLCD output site MB
- */
- ldr x4, =SYSREGS_BASE
- ldr w5, =(1 << 31) | (1 << 30) | (7 << 20) | (0 << 16) // START|WRITE|MUXFPGA|SITE_MB
- str wzr, [x4, #0xa0] // V2M_SYS_CFGDATA
- str w5, [x4, #0xa4] // V2M_SYS_CFGCTRL
-
- // set up the arch timer frequency
- //ldr x0, =CNTFRQ
- //msr cntfrq_el0, x0
-
- /*
- * Primary CPU
- */
- ldr x0, =PHYS_OFFSET + 0x8000000 // device tree blob
- ldr x6, =PHYS_OFFSET + 0x80000 // kernel start address
- br x6
-
- .ltorg
-
- .org 0x200
+++ /dev/null
-# Copyright (c) 2019-2020 ARM Limited
-# All rights reserved.
-#
-# Redistribution and use in source and binary forms, with or without
-# modification, are permitted provided that the following conditions are
-# met: redistributions of source code must retain the above copyright
-# notice, this list of conditions and the following disclaimer;
-# redistributions in binary form must reproduce the above copyright
-# notice, this list of conditions and the following disclaimer in the
-# documentation and/or other materials provided with the distribution;
-# neither the name of the copyright holders nor the names of its
-# contributors may be used to endorse or promote products derived from
-# this software without specific prior written permission.
-#
-# THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
-# "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
-# LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
-# A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT
-# OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,
-# SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
-# LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
-# DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
-# THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
-# (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
-# OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
-
-CROSS_COMPILE = aarch64-linux-gnu-
-CC = $(CROSS_COMPILE)gcc
-LD = $(CROSS_COMPILE)ld
-
-BUILDDIR = .
-DESTDIR = $(error Please set DESTDIR to wanted installation directory)
-
-CFLAGS = -march=armv8-a
-CPPFLAGS = -DPHYS_OFFSET=0x80000000 -DCNTFRQ=0x01800000 \
- -DUART_BASE=0x1c090000 -DSYSREGS_BASE=0x1c010000 \
- -DGIC_DIST_BASE=0x2c001000 -Dkernel=0x80080000 \
- -Dmbox=0x8000fff8 -Ddtb=0x80000100
-
-LDFLAGS = -N -Ttext 0x00000010 -non_shared -static
-
-.PHONY: all clean install mkdir
-
-all: mkdir $(BUILDDIR)/boot_emm.arm64 \
- $(BUILDDIR)/boot.arm64 \
- $(BUILDDIR)/boot_v2.arm64
-
-#v1 has a GIC V2
-$(BUILDDIR)/boot_emm.o: CPPFLAGS += -UGICV3 -DGIC_CPU_BASE=0x2c002000
-$(BUILDDIR)/boot.o: CPPFLAGS += -UGICV3 -DGIC_CPU_BASE=0x2c002000
-
-#V2 has a GIC V3
-$(BUILDDIR)/boot_v2.o: CPPFLAGS += -DGICV3 -DGIC_REDIST_BASE=0x2c010000
-
-$(BUILDDIR)/%.arm64: $(BUILDDIR)/%.o
- $(LD) -o $@ $< $(LDFLAGS)
-
-$(BUILDDIR)/%.o: boot.S
- $(CC) $(CPPFLAGS) -c $< -o $@ $(CFLAGS)
-
-install:
- mkdir -p $(DESTDIR)
- install -m 644 $(BUILDDIR)/boot_emm.arm64 \
- $(BUILDDIR)/boot.arm64 \
- $(BUILDDIR)/boot_v2.arm64 \
- $(DESTDIR)/.
-
-mkdir:
- mkdir -p $(BUILDDIR)
-
-clean:
- rm -f $(BUILDDIR)/*.o
- rm -f $(BUILDDIR)/boot_emm.arm64 $(BUILDDIR)/boot.arm64 $(BUILDDIR)/boot_v2.arm64
--- /dev/null
+# Copyright (c) 2011, 2020 ARM Limited
+# All rights reserved.
+#
+# The license below extends only to copyright in the software and shall
+# not be construed as granting a license to any other intellectual
+# property including but not limited to intellectual property relating
+# to a hardware implementation of the functionality of the software
+# licensed hereunder. You may use the software subject to the license
+# terms below provided that you ensure that this notice is replicated
+# unmodified and in its entirety in all distributions of the software,
+# modified or unmodified, in source code or in binary form.
+#
+# Redistribution and use in source and binary forms, with or without
+# modification, are permitted provided that the following conditions are
+# met: redistributions of source code must retain the above copyright
+# notice, this list of conditions and the following disclaimer;
+# redistributions in binary form must reproduce the above copyright
+# notice, this list of conditions and the following disclaimer in the
+# documentation and/or other materials provided with the distribution;
+# neither the name of the copyright holders nor the names of its
+# contributors may be used to endorse or promote products derived from
+# this software without specific prior written permission.
+#
+# THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
+# "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
+# LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
+# A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT
+# OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,
+# SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
+# LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
+# DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
+# THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
+# (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
+# OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+#
+# Authors: Ali Saidi
+# Prakash Ramrakhyani
+
+
+# Need to have CROSS_COMPILE set to /path/to/bin/arm-unknown-linux-gnu-
+# or have arm-unknown-linux-gnu in your path
+
+CROSS_COMPILE?=arm-linux-gnueabi-
+
+CC=$(CROSS_COMPILE)gcc
+CPP=$(CROSS_COMPILE)g++
+LD=$(CROSS_COMPILE)ld
+
+all: boot.arm boot_emm.arm
+
+boot.o: simple.S
+ $(CC) -mfloat-abi=softfp -march=armv7-a -fno-builtin -nostdinc -o $@ -c $<
+
+boot.arm: boot.o
+ $(LD) -o $@ -N -Ttext 0x00000010 $< -non_shared -static
+boot_emm.arm: boot.o
+ $(LD) -o $@ -N -Ttext 0x00000010 $< -non_shared -static
+
+
+clean:
+ $(RM) -f *.o boot.arm boot_emm.arm
+
+.PHONY: all clean
--- /dev/null
+/*
+ * Copyright (c) 2010 ARM Limited
+ * All rights reserved
+ *
+ * The license below extends only to copyright in the software and shall
+ * not be construed as granting a license to any other intellectual
+ * property including but not limited to intellectual property relating
+ * to a hardware implementation of the functionality of the software
+ * licensed hereunder. You may use the software subject to the license
+ * terms below provided that you ensure that this notice is replicated
+ * unmodified and in its entirety in all distributions of the software,
+ * modified or unmodified, in source code or in binary form.
+ *
+ * Redistribution and use in source and binary forms, with or without
+ * modification, are permitted provided that the following conditions are
+ * met: redistributions of source code must retain the above copyright
+ * notice, this list of conditions and the following disclaimer;
+ * redistributions in binary form must reproduce the above copyright
+ * notice, this list of conditions and the following disclaimer in the
+ * documentation and/or other materials provided with the distribution;
+ * neither the name of the copyright holders nor the names of its
+ * contributors may be used to endorse or promote products derived from
+ * this software without specific prior written permission.
+ *
+ * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
+ * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
+ * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
+ * A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT
+ * OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,
+ * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
+ * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
+ * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
+ * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
+ * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
+ * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+ *
+ * Authors: Ali Saidi
+ */
+
+/*************************************************************************
+ * Super simple bootloader
+ * Preserve loaded values that we need to pass to the kernel (r0, r1, r2)
+ * Additionally M5 puts the kernel start address in r3
+ *
+ * Upon executing this code:
+ * r0 = 0, r1 = machine number, r2 = atags ptr
+ * r3 = kernel start address, r4 = GIC address, r5 = flag register address
+ *
+ * CPU 0 should branch to the kernel start address and it's done with
+ * the boot loader. Other CPUs need to start in a wfi loop. When CPU0 sends
+ * an IPI the slave CPUs reads a register which CPU0 has programmed with the
+ * boot address for the secondary cpu
+ **************************************************************************/
+.text
+.globl _start
+.extern main
+_start:
+_entry:
+ b bootldr // All the interrupt vectors jump to the boot loader
+ b bootldr
+ b bootldr
+ b bootldr
+ b bootldr
+ b bootldr
+ b bootldr
+ b bootldr
+ b bootldr
+
+bootldr:
+ mrc p15, 0, r8, c0, c0, 5 // get the MPIDR register
+ bics r8, r8, #0xff000000 // isolate the lower 24 bits (affinity levels)
+ bxeq r3 // if it's 0 (CPU 0), branch to kernel
+ mov r8, #1
+ str r8, [r4, #0] // Enable CPU interface on GIC
+ wfi // wait for an interrupt
+pen:
+ ldr r8, [r5] // load the value
+ movs r8, r8 // set the flags on this value
+ beq pen // if it's zero try again
+ bx r8 // Jump to where we've been told
+ bkpt // We should never get here
--- /dev/null
+/*
+ * Copyright (c) 2012 ARM Limited
+ * All rights reserved
+ *
+ * The license below extends only to copyright in the software and shall
+ * not be construed as granting a license to any other intellectual
+ * property including but not limited to intellectual property relating
+ * to a hardware implementation of the functionality of the software
+ * licensed hereunder. You may use the software subject to the license
+ * terms below provided that you ensure that this notice is replicated
+ * unmodified and in its entirety in all distributions of the software,
+ * modified or unmodified, in source code or in binary form.
+ *
+ * Redistribution and use in source and binary forms, with or without
+ * modification, are permitted provided that the following conditions are
+ * met: redistributions of source code must retain the above copyright
+ * notice, this list of conditions and the following disclaimer;
+ * redistributions in binary form must reproduce the above copyright
+ * notice, this list of conditions and the following disclaimer in the
+ * documentation and/or other materials provided with the distribution;
+ * neither the name of the copyright holders nor the names of its
+ * contributors may be used to endorse or promote products derived from
+ * this software without specific prior written permission.
+ *
+ * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
+ * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
+ * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
+ * A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT
+ * OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,
+ * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
+ * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
+ * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
+ * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
+ * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
+ * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+ *
+ */
+
+ .text
+
+ .globl _start
+_start:
+ /*
+ * EL3 initialisation
+ */
+ mrs x0, CurrentEL
+ cmp x0, #0xc // EL3?
+ b.ne start_ns // skip EL3 initialisation
+
+ mov x0, #0x30 // RES1
+ orr x0, x0, #(1 << 0) // Non-secure EL1
+ orr x0, x0, #(1 << 8) // HVC enable
+ orr x0, x0, #(1 << 10) // 64-bit EL2
+ msr scr_el3, x0
+
+ msr cptr_el3, xzr // Disable copro. traps to EL3
+
+ ldr x0, =CNTFRQ
+ msr cntfrq_el0, x0
+
+ /*
+ * Check for the primary CPU to avoid a race on the distributor
+ * registers.
+ */
+ mrs x0, mpidr_el1
+ // ARM MPIDR_EL1 bytes: Aff3 (AArch64), Stuff, Aff2, Aff1, Aff0
+ // Test the the MPIDR_EL1 register against 0xff00ffffff to
+ // extract the primary CPU.
+ ldr x1, =0xff00ffffff
+#ifdef GICV3
+ and x2, x0, #0xff // use Aff0 as cpuid for now...
+ tst x0, x1 // check for cpuid==zero
+ b.ne 1f // secondary CPU
+
+ ldr x1, =GIC_DIST_BASE // GICD_CTLR
+ mov w0, #7 // EnableGrp0 | EnableGrp1NS | EnableGrp1S
+ str w0, [x1]
+
+
+1: ldr x1, =GIC_REDIST_BASE + 0x10000 + 0x80 // GICR_IGROUPR0
+ // 128K for each redistributor, 256K strided...
+ mov x3, #1 << 18 // GICv4
+ mul x3, x3, x2
+ add x1, x1, x3
+ mov w0, #~0 // Grp1 interrupts
+ str w0, [x1], #4
+ b.ne 2f // Only local interrupts for secondary CPUs
+ ldr x1, =GIC_DIST_BASE + 0x84 // GICD_IGROUPR
+ str w0, [x1], #4
+ str w0, [x1], #4
+ str w0, [x1], #4
+
+ /* SRE & Disable IRQ/FIQ Bypass & Allow EL2 access to ICC_SRE_EL2 */
+2: mrs x10, S3_6_C12_C12_5 // read ICC_SRE_EL3
+ orr x10, x10, #0xf // enable 0xf
+ msr S3_6_C12_C12_5, x10 // write ICC_SRE_EL3
+ isb
+
+ mov x0, #1
+ msr S3_0_c12_c12_6, x0 // ICC_IGRPEN0_EL1 Enable
+ msr S3_0_C12_C12_7, x0 // ICC_IGRPEN1_EL1 Enable
+#else
+ tst x0, x1 // check for cpuid==zero
+ b.ne 1f // secondary CPU
+
+ ldr x1, =GIC_DIST_BASE // GICD_CTLR
+ mov w0, #3 // EnableGrp0 | EnableGrp1
+ str w0, [x1]
+
+1: ldr x1, =GIC_DIST_BASE + 0x80 // GICD_IGROUPR
+ mov w0, #~0 // Grp1 interrupts
+ str w0, [x1], #4
+ b.ne 2f // Only local interrupts for secondary CPUs
+ str w0, [x1], #4
+ str w0, [x1], #4
+
+2: ldr x1, =GIC_CPU_BASE // GICC_CTLR
+ ldr w0, [x1]
+ mov w0, #3 // EnableGrp0 | EnableGrp1
+ str w0, [x1]
+
+ mov w0, #1 << 7 // allow NS access to GICC_PMR
+ str w0, [x1, #4] // GICC_PMR
+#endif
+
+ msr sctlr_el2, xzr
+
+ /*
+ * Prepare the switch to the EL2_SP1 mode from EL3
+ */
+ ldr x0, =start_ns // Return after mode switch
+ mov x1, #0x3c9 // EL2_SP1 | D | A | I | F
+ msr elr_el3, x0
+ msr spsr_el3, x1
+ eret
+
+start_ns:
+ /*
+ * Kernel parameters
+ */
+ mov x0, xzr
+ mov x1, xzr
+ mov x2, xzr
+ mov x3, xzr
+
+ mrs x4, mpidr_el1
+ // ARM MPIDR_EL1 bytes: Aff3 (AArch64), Stuff, Aff2, Aff1, Aff0
+ // Test the the MPIDR_EL1 register against 0xff00ffffff to
+ // extract the primary CPU.
+ ldr x1, =0xff00ffffff
+ tst x4, x1 // check for cpuid==zero
+ mov x1, xzr // load previous 'xzr' value back to x1
+ b.eq 2f // secondary CPU
+
+ /*
+ * Secondary CPUs
+ */
+1: wfe
+ ldr x4, =PHYS_OFFSET + 0xfff8
+ ldr x4, [x4]
+ cbz x4, 1b
+ br x4 // branch to the given address
+
+2:
+ /*
+ * UART initialisation (38400 8N1)
+ */
+ ldr x4, =UART_BASE // UART base
+ mov w5, #0x10 // ibrd
+ str w5, [x4, #0x24]
+ mov w5, #0xc300
+ orr w5, w5, #0x0001 // cr
+ str w5, [x4, #0x30]
+
+ /*
+ * CLCD output site MB
+ */
+ ldr x4, =SYSREGS_BASE
+ ldr w5, =(1 << 31) | (1 << 30) | (7 << 20) | (0 << 16) // START|WRITE|MUXFPGA|SITE_MB
+ str wzr, [x4, #0xa0] // V2M_SYS_CFGDATA
+ str w5, [x4, #0xa4] // V2M_SYS_CFGCTRL
+
+ // set up the arch timer frequency
+ //ldr x0, =CNTFRQ
+ //msr cntfrq_el0, x0
+
+ /*
+ * Primary CPU
+ */
+ ldr x0, =PHYS_OFFSET + 0x8000000 // device tree blob
+ ldr x6, =PHYS_OFFSET + 0x80000 // kernel start address
+ br x6
+
+ .ltorg
+
+ .org 0x200
--- /dev/null
+# Copyright (c) 2019-2020 ARM Limited
+# All rights reserved.
+#
+# Redistribution and use in source and binary forms, with or without
+# modification, are permitted provided that the following conditions are
+# met: redistributions of source code must retain the above copyright
+# notice, this list of conditions and the following disclaimer;
+# redistributions in binary form must reproduce the above copyright
+# notice, this list of conditions and the following disclaimer in the
+# documentation and/or other materials provided with the distribution;
+# neither the name of the copyright holders nor the names of its
+# contributors may be used to endorse or promote products derived from
+# this software without specific prior written permission.
+#
+# THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
+# "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
+# LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
+# A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT
+# OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,
+# SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
+# LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
+# DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
+# THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
+# (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
+# OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+
+CROSS_COMPILE = aarch64-linux-gnu-
+CC = $(CROSS_COMPILE)gcc
+LD = $(CROSS_COMPILE)ld
+
+BUILDDIR = .
+DESTDIR = $(error Please set DESTDIR to wanted installation directory)
+
+CFLAGS = -march=armv8-a
+CPPFLAGS = -DPHYS_OFFSET=0x80000000 -DCNTFRQ=0x01800000 \
+ -DUART_BASE=0x1c090000 -DSYSREGS_BASE=0x1c010000 \
+ -DGIC_DIST_BASE=0x2c001000 -Dkernel=0x80080000 \
+ -Dmbox=0x8000fff8 -Ddtb=0x80000100
+
+LDFLAGS = -N -Ttext 0x00000010 -non_shared -static
+
+.PHONY: all clean install mkdir
+
+all: mkdir $(BUILDDIR)/boot_emm.arm64 \
+ $(BUILDDIR)/boot.arm64 \
+ $(BUILDDIR)/boot_v2.arm64
+
+#v1 has a GIC V2
+$(BUILDDIR)/boot_emm.o: CPPFLAGS += -UGICV3 -DGIC_CPU_BASE=0x2c002000
+$(BUILDDIR)/boot.o: CPPFLAGS += -UGICV3 -DGIC_CPU_BASE=0x2c002000
+
+#V2 has a GIC V3
+$(BUILDDIR)/boot_v2.o: CPPFLAGS += -DGICV3 -DGIC_REDIST_BASE=0x2c010000
+
+$(BUILDDIR)/%.arm64: $(BUILDDIR)/%.o
+ $(LD) -o $@ $< $(LDFLAGS)
+
+$(BUILDDIR)/%.o: boot.S
+ $(CC) $(CPPFLAGS) -c $< -o $@ $(CFLAGS)
+
+install:
+ mkdir -p $(DESTDIR)
+ install -m 644 $(BUILDDIR)/boot_emm.arm64 \
+ $(BUILDDIR)/boot.arm64 \
+ $(BUILDDIR)/boot_v2.arm64 \
+ $(DESTDIR)/.
+
+mkdir:
+ mkdir -p $(BUILDDIR)
+
+clean:
+ rm -f $(BUILDDIR)/*.o
+ rm -f $(BUILDDIR)/boot_emm.arm64 $(BUILDDIR)/boot.arm64 $(BUILDDIR)/boot_v2.arm64
+++ /dev/null
-# Copyright (c) 2011, 2020 ARM Limited
-# All rights reserved.
-#
-# The license below extends only to copyright in the software and shall
-# not be construed as granting a license to any other intellectual
-# property including but not limited to intellectual property relating
-# to a hardware implementation of the functionality of the software
-# licensed hereunder. You may use the software subject to the license
-# terms below provided that you ensure that this notice is replicated
-# unmodified and in its entirety in all distributions of the software,
-# modified or unmodified, in source code or in binary form.
-#
-# Redistribution and use in source and binary forms, with or without
-# modification, are permitted provided that the following conditions are
-# met: redistributions of source code must retain the above copyright
-# notice, this list of conditions and the following disclaimer;
-# redistributions in binary form must reproduce the above copyright
-# notice, this list of conditions and the following disclaimer in the
-# documentation and/or other materials provided with the distribution;
-# neither the name of the copyright holders nor the names of its
-# contributors may be used to endorse or promote products derived from
-# this software without specific prior written permission.
-#
-# THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
-# "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
-# LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
-# A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT
-# OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,
-# SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
-# LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
-# DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
-# THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
-# (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
-# OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
-#
-# Authors: Ali Saidi
-# Prakash Ramrakhyani
-
-
-# Need to have CROSS_COMPILE set to /path/to/bin/arm-unknown-linux-gnu-
-# or have arm-unknown-linux-gnu in your path
-
-CROSS_COMPILE?=arm-linux-gnueabi-
-
-CC=$(CROSS_COMPILE)gcc
-CPP=$(CROSS_COMPILE)g++
-LD=$(CROSS_COMPILE)ld
-
-all: boot.arm boot_emm.arm
-
-boot.o: simple.S
- $(CC) -mfloat-abi=softfp -march=armv7-a -fno-builtin -nostdinc -o $@ -c $<
-
-boot.arm: boot.o
- $(LD) -o $@ -N -Ttext 0x00000010 $< -non_shared -static
-boot_emm.arm: boot.o
- $(LD) -o $@ -N -Ttext 0x00000010 $< -non_shared -static
-
-
-clean:
- $(RM) -f *.o boot.arm boot_emm.arm
-
-.PHONY: all clean
+++ /dev/null
-/*
- * Copyright (c) 2010 ARM Limited
- * All rights reserved
- *
- * The license below extends only to copyright in the software and shall
- * not be construed as granting a license to any other intellectual
- * property including but not limited to intellectual property relating
- * to a hardware implementation of the functionality of the software
- * licensed hereunder. You may use the software subject to the license
- * terms below provided that you ensure that this notice is replicated
- * unmodified and in its entirety in all distributions of the software,
- * modified or unmodified, in source code or in binary form.
- *
- * Redistribution and use in source and binary forms, with or without
- * modification, are permitted provided that the following conditions are
- * met: redistributions of source code must retain the above copyright
- * notice, this list of conditions and the following disclaimer;
- * redistributions in binary form must reproduce the above copyright
- * notice, this list of conditions and the following disclaimer in the
- * documentation and/or other materials provided with the distribution;
- * neither the name of the copyright holders nor the names of its
- * contributors may be used to endorse or promote products derived from
- * this software without specific prior written permission.
- *
- * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
- * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
- * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
- * A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT
- * OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,
- * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
- * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
- * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
- * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
- * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
- * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
- *
- * Authors: Ali Saidi
- */
-
-/*************************************************************************
- * Super simple bootloader
- * Preserve loaded values that we need to pass to the kernel (r0, r1, r2)
- * Additionally M5 puts the kernel start address in r3
- *
- * Upon executing this code:
- * r0 = 0, r1 = machine number, r2 = atags ptr
- * r3 = kernel start address, r4 = GIC address, r5 = flag register address
- *
- * CPU 0 should branch to the kernel start address and it's done with
- * the boot loader. Other CPUs need to start in a wfi loop. When CPU0 sends
- * an IPI the slave CPUs reads a register which CPU0 has programmed with the
- * boot address for the secondary cpu
- **************************************************************************/
-.text
-.globl _start
-.extern main
-_start:
-_entry:
- b bootldr // All the interrupt vectors jump to the boot loader
- b bootldr
- b bootldr
- b bootldr
- b bootldr
- b bootldr
- b bootldr
- b bootldr
- b bootldr
-
-bootldr:
- mrc p15, 0, r8, c0, c0, 5 // get the MPIDR register
- bics r8, r8, #0xff000000 // isolate the lower 24 bits (affinity levels)
- bxeq r3 // if it's 0 (CPU 0), branch to kernel
- mov r8, #1
- str r8, [r4, #0] // Enable CPU interface on GIC
- wfi // wait for an interrupt
-pen:
- ldr r8, [r5] // load the value
- movs r8, r8 // set the flags on this value
- beq pen // if it's zero try again
- bx r8 // Jump to where we've been told
- bkpt // We should never get here
["cp"] + glob(dt_dir + "/*dtb") + [binaries_dir])
# Build bootloaders arm64
-bootloader_arm64_dir = gem5_dir + "/system/arm/aarch64_bootloader"
+bootloader_arm64_dir = gem5_dir + "/system/arm/bootloader/arm64"
run_cmd("compile arm64 bootloader",
bootloader_arm64_dir,
["make"])
["cp", "boot.arm64", "boot_emm.arm64", "boot_v2.arm64", binaries_dir])
# Build bootloaders arm
-bootloader_arm_dir = gem5_dir + "/system/arm/simple_bootloader"
+bootloader_arm_dir = gem5_dir + "/system/arm/bootloader/arm"
run_cmd("compile arm bootloader",
bootloader_arm_dir,
["make"])
projects / gem5.git / commitdiff