hdl.mem: fix naming of registers inside unnamed memories.

Before this commit, `None` would leak into the vcd file with pysim.

diff --git a/nmigen/hdl/mem.py b/nmigen/hdl/mem.py
index 2111ecc193f29dd9038c1c2977163492cc268adc..45836cbed588832585e87be2ae3bdd11f9635395 100644 (file)
--- a/nmigen/hdl/mem.py
+++ b/nmigen/hdl/mem.py
@@ -27,7 +27,8 @@ class Memory:
         self._array = Array()
         if simulate:
             for addr in range(self.depth):
-                self._array.append(Signal(self.width, name="{}({})".format(name, addr)))
+                self._array.append(Signal(self.width, name="{}({})"
+                                          .format(name or "memory", addr)))
 
         self.init = init