interface Get#(Bit#(1)) ncs_o;
endinterface
- interface Ifc_qspi;
+ interface Ifc_mqspi;
interface QSPI_out out;
interface AXI4_Lite_Slave_IFC#(`PADDR,`Reg_width,`USERSPACE) slave;
method Bit#(6) interrupts; // 0=TOF, 1=SMF, 2=Threshold, 3=TCF, 4=TEF 5 = request_ready
Idle=6} Phase deriving (Bits,Eq,FShow);
(*synthesize*)
- module mkqspi(Ifc_qspi);
+ module mkqspi(Ifc_mqspi);
AXI4_Lite_Slave_Xactor_IFC #(`PADDR, `Reg_width, `USERSPACE) s_xactor <- mkAXI4_Lite_Slave_Xactor;
/*************** List of implementation defined Registers *****************/
interface Get#(Bit#(1)) ncs_o;
endinterface
- interface Ifc_spi;
+ interface Ifc_mspi;
interface SPI_out out;
interface AXI4_Lite_Slave_IFC#(`PADDR,`Reg_width,`USERSPACE) slave;
// 0=TOF, 1=SMF, 2=Threshold, 3=TCF, 4=TEF 5 = request_ready
(*synthesize*)
- module mkspi(Ifc_spi);
+ module mkspi(Ifc_mspi);
Ifc_qspi qspi <- mkqspi();