i915: Drop gen4+ code from the forked clear code.

Reviewed-by: Ian Romanick <ian.d.romanick@intel.com>
Reviewed-by: Chad Versace <chad.versace@linux.intel.com>

diff --git a/src/mesa/drivers/dri/i915/intel_clear.c b/src/mesa/drivers/dri/i915/intel_clear.c
index 331635148f61359afdb551d5ff73b18616265488..96d9c8fe68284ab95c14cb86ff7d4b9affa2e8d1 100644 (file)
--- a/src/mesa/drivers/dri/i915/intel_clear.c
+++ b/src/mesa/drivers/dri/i915/intel_clear.c
@@ -89,9 +89,6 @@ intelClear(struct gl_context *ctx, GLbitfield mask)
    struct intel_renderbuffer *irb;
    int i;
 
-   if (!_mesa_check_conditional_render(ctx))
-      return;
-
    if (mask & (BUFFER_BIT_FRONT_LEFT | BUFFER_BIT_FRONT_RIGHT)) {
       intel->front_buffer_dirty = true;
    }
@@ -116,7 +113,7 @@ intelClear(struct gl_context *ctx, GLbitfield mask)
    }
 
    /* HW color buffers (front, back, aux, generic FBO, etc) */
-   if (intel->gen < 6 && colorMask == ~0) {
+   if (colorMask == ~0) {
       /* clear all R,G,B,A */
       blit_mask |= (mask & BUFFER_BITS_COLOR);
    }
@@ -143,12 +140,6 @@ intelClear(struct gl_context *ctx, GLbitfield mask)
             */
             tri_mask |= BUFFER_BIT_STENCIL;
          }
-        else if (intel->has_separate_stencil &&
-              stencilRegion->tiling == I915_TILING_NONE) {
-           /* The stencil buffer is actually W tiled, which the hardware
-            * cannot blit to. */
-           tri_mask |= BUFFER_BIT_STENCIL;
-        }
          else {
             /* clearing all stencil bits, use blitting */
             blit_mask |= BUFFER_BIT_STENCIL;