Added "techmap -map %{design-name}"

diff --git a/kernel/rtlil.cc b/kernel/rtlil.cc
index 83bbd7b17012b02c7355aa4ade50bdc0293635cc..f864d88c09be91ae75fc0c201758499432a1ca58 100644 (file)
--- a/kernel/rtlil.cc
+++ b/kernel/rtlil.cc
@@ -219,6 +219,11 @@ void RTLIL::Selection::optimize(RTLIL::Design *design)
        }
 }
 
+RTLIL::Design::Design()
+{
+       refcount_modules_ = 0;
+}
+
 RTLIL::Design::~Design()
 {
        for (auto it = modules_.begin(); it != modules_.end(); it++)

diff --git a/kernel/rtlil.h b/kernel/rtlil.h
index e8d05e7e4407ae637e3ac4843eee4d5918735649..1f25542f3fc0bf15021b28e78239dcb6936f21fa 100644 (file)
--- a/kernel/rtlil.h
+++ b/kernel/rtlil.h
@@ -352,11 +352,16 @@ struct RTLIL::Design
        std::map<RTLIL::IdString, RTLIL::Selection> selection_vars;
        std::string selected_active_module;
 
+       Design();
        ~Design();
 
        RTLIL::ObjRange<RTLIL::Module*> modules();
        RTLIL::Module *module(RTLIL::IdString name);
 
+       bool has(RTLIL::IdString id) const {
+               return modules_.count(id) != 0;
+       }
+
        void add(RTLIL::Module *module);
        RTLIL::Module *addModule(RTLIL::IdString name);
        void remove(RTLIL::Module *module);

diff --git a/passes/techmap/extract.cc b/passes/techmap/extract.cc
index 9c5fa7f71d751c269eca639f38e2bb3fed0ebc91..19d323341e6b597b1c9635baa27cceee70ce78f3 100644 (file)
--- a/passes/techmap/extract.cc
+++ b/passes/techmap/extract.cc
@@ -603,9 +603,9 @@ struct ExtractPass : public Pass {
                                                delete map;
                                                log_cmd_error("Can't saved design `%s'.\n", filename.c_str()+1);
                                        }
-                                       for (auto &it : saved_designs.at(filename.substr(1))->modules_)
-                                               if (!map->modules_.count(it.first))
-                                                       map->modules_[it.first] = it.second->clone();
+                                       for (auto mod : saved_designs.at(filename.substr(1))->modules())
+                                               if (!map->has(mod->name))
+                                                       map->add(mod->clone());
                                }
                                else
                                {

diff --git a/passes/techmap/techmap.cc b/passes/techmap/techmap.cc
index 5a69baca5b35c1b6ac0dd5ce7959aca10799d01f..0ae5220e062498c54d2cd07c7001e5771eb53cd2 100644 (file)
--- a/passes/techmap/techmap.cc
+++ b/passes/techmap/techmap.cc
@@ -656,13 +656,22 @@ struct TechmapPass : public Pass {
                        Frontend::frontend_call(map, f, "<stdcells.v>", verilog_frontend);
                        fclose(f);
                } else
-                       for (auto &fn : map_files) {
-                               FILE *f = fopen(fn.c_str(), "rt");
-                               if (f == NULL)
-                                       log_cmd_error("Can't open map file `%s'\n", fn.c_str());
-                               Frontend::frontend_call(map, f, fn, (fn.size() > 3 && fn.substr(fn.size()-3) == ".il") ? "ilang" : verilog_frontend);
-                               fclose(f);
-                       }
+                       for (auto &fn : map_files)
+                               if (fn.substr(0, 1) == "%") {
+                                       if (!saved_designs.count(fn.substr(1))) {
+                                               delete map;
+                                               log_cmd_error("Can't saved design `%s'.\n", fn.c_str()+1);
+                                       }
+                                       for (auto mod : saved_designs.at(fn.substr(1))->modules())
+                                               if (!map->has(mod->name))
+                                                       map->add(mod->clone());
+                               } else {
+                                       FILE *f = fopen(fn.c_str(), "rt");
+                                       if (f == NULL)
+                                               log_cmd_error("Can't open map file `%s'\n", fn.c_str());
+                                       Frontend::frontend_call(map, f, fn, (fn.size() > 3 && fn.substr(fn.size()-3) == ".il") ? "ilang" : verilog_frontend);
+                                       fclose(f);
+                               }
 
                std::map<RTLIL::IdString, RTLIL::Module*> modules_new;
                for (auto &it : map->modules_) {