(no commit message)

diff --git a/openpower/sv/SimpleV_rationale.mdwn b/openpower/sv/SimpleV_rationale.mdwn
index db230e0b281368dd0b829ddf5267058d0da25e06..11f27a060588a3737011ec84c0adc9b98a064430 100644 (file)
--- a/openpower/sv/SimpleV_rationale.mdwn
+++ b/openpower/sv/SimpleV_rationale.mdwn
@@ -624,7 +624,7 @@ accesses scheduled underway and interleaved in a time-sliced
 fashion with an FPU that is correspondingly 8 times faster than
 the Coherent Memory accesses.
 
-This design is almost identical to the early Vector Processors
+This design is reminiscent of the early Vector Processors
 of the late 1950s and early 1960s, which also critically relied
 on implicit auto-increment addressing.
 The [CDC STAR-100](https://en.m.wikipedia.org/wiki/CDC_STAR-100)
@@ -632,10 +632,11 @@ for example was specifically designed as a Memory-to-Memory Vector
 Processor. The barrel-architecture of Snitch neatly
 solves one of the inherent problems of those early designs (a mismatch
 with memory
-speed) and the presence of a full register file caters for a
+speed) and the presence of a full register file (non-tagged,
+normal, standard scalar registers) caters for a
 second limitation of pure Memory-based Vector Processors: temporary
 variables needed in the computation of intermediate results, which
-also were put in memory, put
+also had to go through memory, put
 an awfully high artificial load on Memory bandwidth.
 
 The similarity to SVP64 should be clear: SVP64 Prefixing and the