[xcc,sim,opcodes] added rvc conditional branches

diff --git a/riscv/decode.h b/riscv/decode.h
index a49137a3f359f5d4b699db74e58e16fcd5a116de..f411c10bec0468b14e0312fc099e67a42c24ed34 100644 (file)
--- a/riscv/decode.h
+++ b/riscv/decode.h
@@ -216,12 +216,15 @@ private:
 #define CIMM6 ((int32_t)((insn.bits >> 10) & 0x3f) << 26 >> 26)
 #define CIMM5 ((int32_t)((insn.bits >> 5) & 0x1f) << 27 >> 27)
 #define CIMM10 ((int32_t)((insn.bits >> 5) & 0x3ff) << 22 >> 22)
+#define CBRANCH_TARGET (pc + (CIMM5 << BRANCH_ALIGN_BITS))
 #define CJUMP_TARGET (pc + (CIMM10 << JUMP_ALIGN_BITS))
 
-static const uint8_t rvc_regmap[8] = { 20, 21, 2, 3, 4, 5, 6, 7 };
-#define CRDS do_writeback(XPR, rvc_regmap[(insn.bits >> 13) & 0x7])
-#define CRS1S XPR[rvc_regmap[(insn.bits >> 10) & 0x7]]
-#define CRS2S XPR[rvc_regmap[(insn.bits >> 13) & 0x7]]
+static const int rvc_rs1_regmap[8] = { 20, 21, 2, 3, 4, 5, 6, 7 };
+#define rvc_rd_regmap rvc_rs1_regmap
+static const int rvc_rs2_regmap[8] = { 20, 21, 2, 3, 4, 5, 6, 0 };
+#define CRDS do_writeback(XPR, rvc_rd_regmap[(insn.bits >> 13) & 0x7])
+#define CRS1S XPR[rvc_rs1_regmap[(insn.bits >> 10) & 0x7]]
+#define CRS2S XPR[rvc_rs2_regmap[(insn.bits >> 13) & 0x7]]
 
 // vector stuff
 #define VL vl

diff --git a/riscv/execute.h b/riscv/execute.h
index 1005a5351862de977f4c6beee6ed6bd24b7fe56c..fbc595a8d199b019f8e51623906e3e4c4ec38a83 100644 (file)
--- a/riscv/execute.h
+++ b/riscv/execute.h
@@ -659,6 +659,16 @@ switch((insn.bits >> 0x0) & 0x7f)
     }
     break;
   }
+  case 0x10:
+  {
+    #include "insns/c_beq.h"
+    break;
+  }
+  case 0x11:
+  {
+    #include "insns/c_bne.h"
+    break;
+  }
   case 0x13:
   {
     switch((insn.bits >> 0x7) & 0x7)
@@ -1127,6 +1137,16 @@ switch((insn.bits >> 0x0) & 0x7f)
     }
     break;
   }
+  case 0x30:
+  {
+    #include "insns/c_beq.h"
+    break;
+  }
+  case 0x31:
+  {
+    #include "insns/c_bne.h"
+    break;
+  }
   case 0x33:
   {
     switch((insn.bits >> 0x7) & 0x7)
@@ -1647,6 +1667,16 @@ switch((insn.bits >> 0x0) & 0x7f)
     }
     break;
   }
+  case 0x50:
+  {
+    #include "insns/c_beq.h"
+    break;
+  }
+  case 0x51:
+  {
+    #include "insns/c_bne.h"
+    break;
+  }
   case 0x53:
   {
     switch((insn.bits >> 0x7) & 0x7)
@@ -2308,6 +2338,16 @@ switch((insn.bits >> 0x0) & 0x7f)
     #include "insns/jal.h"
     break;
   }
+  case 0x70:
+  {
+    #include "insns/c_beq.h"
+    break;
+  }
+  case 0x71:
+  {
+    #include "insns/c_bne.h"
+    break;
+  }
   case 0x73:
   {
     switch((insn.bits >> 0x7) & 0x7)

diff --git a/riscv/insns/c_beq.h b/riscv/insns/c_beq.h
new file mode 100644 (file)
index 0000000..4ceaba2
--- /dev/null
+++ b/riscv/insns/c_beq.h
@@ -0,0 +1,3 @@
+require_rvc;
+if(cmp_trunc(CRS1S) == cmp_trunc(CRS2S))
+  npc = CBRANCH_TARGET;

diff --git a/riscv/insns/c_bne.h b/riscv/insns/c_bne.h
new file mode 100644 (file)
index 0000000..59f257b
--- /dev/null
+++ b/riscv/insns/c_bne.h
@@ -0,0 +1,3 @@
+require_rvc;
+if(cmp_trunc(CRS1S) != cmp_trunc(CRS2S))
+  npc = CBRANCH_TARGET;