False),
BoolVariable('USE_POSIX_CLOCK', 'Use POSIX Clocks', have_posix_clock),
BoolVariable('USE_FENV', 'Use <fenv.h> IEEE mode control', have_fenv),
- BoolVariable('USE_CHECKER', 'Use checker for detailed CPU models', False),
BoolVariable('CP_ANNOTATE', 'Enable critical path annotation capability', False),
)
# These variables get exported to #defines in config/*.hh (see src/SConscript).
export_vars += ['USE_FENV', 'NO_FAST_ALLOC', 'FORCE_FAST_ALLOC',
- 'FAST_ALLOC_STATS', 'SS_COMPATIBLE_FP', 'USE_CHECKER',
+ 'FAST_ALLOC_STATS', 'SS_COMPATIBLE_FP',
'TARGET_ISA', 'CP_ANNOTATE', 'USE_POSIX_CLOCK' ]
###################################################
choices = ["atomic", "timing", "detailed", "inorder",
"arm_detailed"],
help = "type of cpu to run with")
+parser.add_option("--checker", action="store_true");
parser.add_option("-n", "--num-cpus", type="int", default=1)
parser.add_option("--caches", action="store_true")
parser.add_option("--l2cache", action="store_true")
# simulation period
if options.maxinsts:
switch_cpus[i].max_insts_any_thread = options.maxinsts
+ # Add checker cpu if selected
+ if options.checker:
+ switch_cpus[i].addCheckerCpu()
testsys.switch_cpus = switch_cpus
switch_cpu_list = [(testsys.cpu[i], switch_cpus[i]) for i in xrange(np)]
if options.maxinsts:
switch_cpus_1[i].max_insts_any_thread = options.maxinsts
+ # attach the checker cpu if selected
+ if options.checker:
+ switch_cpus[i].addCheckerCpu()
+ switch_cpus_1[i].addCheckerCpu()
+
testsys.switch_cpus = switch_cpus
testsys.switch_cpus_1 = switch_cpus_1
switch_cpu_list = [(testsys.cpu[i], switch_cpus[i]) for i in xrange(np)]
test_sys.cpu = [TestCPUClass(cpu_id=i) for i in xrange(np)]
-CacheConfig.config_cache(options, test_sys)
-
if bm[0]:
mem_size = bm[0].mem()
else:
for i in xrange(np):
if options.fastmem:
test_sys.cpu[i].physmem_port = test_sys.physmem.port
+ if options.checker:
+ test_sys.cpu[i].addCheckerCpu()
+
+CacheConfig.config_cache(options, test_sys)
if buildEnv['TARGET_ISA'] == 'mips':
setMipsOptions(TestCPUClass)
physmem = PhysicalMemory(range=AddrRange("512MB")),
membus = Bus(), mem_mode = test_mem_mode)
-if options.ruby:
- options.use_map = True
- Ruby.create_system(options, system)
- assert(options.num_cpus == len(system.ruby._cpu_ruby_ports))
-else:
- system.system_port = system.membus.slave
- system.physmem.port = system.membus.master
- CacheConfig.config_cache(options, system)
-
for i in xrange(np):
system.cpu[i].workload = multiprocesses[i]
if options.fastmem:
system.cpu[0].physmem_port = system.physmem.port
+ if options.checker:
+ system.cpu[i].addCheckerCpu()
+
+if options.ruby:
+ options.use_map = True
+ Ruby.create_system(options, system)
+ assert(options.num_cpus == len(system.ruby._cpu_ruby_ports))
+else:
+ system.system_port = system.membus.slave
+ system.physmem.port = system.membus.master
+ CacheConfig.config_cache(options, system)
+
root = Root(full_system = False, system = system)
Simulation.run(options, root, system, FutureClass)
# autogenerated files as targets and isa parser itself as a source.
def isa_desc_emitter(target, source, env):
cpu_models = list(env['CPU_MODELS'])
- if env['USE_CHECKER']:
- cpu_models.append('CheckerCPU')
+ cpu_models.append('CheckerCPU')
# Several files are generated from the ISA description.
# We always get the basic decoder and header file.
*/
#include "arch/arm/isa.hh"
-#include "config/use_checker.hh"
+#include "cpu/checker/cpu.hh"
#include "debug/Arm.hh"
#include "debug/MiscRegs.hh"
#include "sim/faults.hh"
#include "sim/stat_control.hh"
#include "sim/system.hh"
-#if USE_CHECKER
-#include "cpu/checker/cpu.hh"
-#endif
-
namespace ArmISA
{
PCState pc = tc->pcState();
pc.nextThumb(cpsr.t);
pc.nextJazelle(cpsr.j);
-#if USE_CHECKER
- tc->pcStateNoRecord(pc);
-#else
- tc->pcState(pc);
-#endif //USE_CHECKER
+
+ // Follow slightly different semantics if a CheckerCPU object
+ // is connected
+ CheckerCPU *checker = tc->getCheckerCpuPtr();
+ if (checker) {
+ tc->pcStateNoRecord(pc);
+ } else {
+ tc->pcState(pc);
+ }
} else if (misc_reg >= MISCREG_CP15_UNIMP_START &&
misc_reg < MISCREG_CP15_END) {
panic("Unimplemented CP15 register %s wrote with %#x.\n",
oc = sys->getThreadContext(x);
oc->getDTBPtr()->allCpusCaching();
oc->getITBPtr()->allCpusCaching();
-#if USE_CHECKER
- CheckerCPU *checker =
- dynamic_cast<CheckerCPU*>(oc->getCheckerCpuPtr());
+
+ // If CheckerCPU is connected, need to notify it.
+ CheckerCPU *checker = oc->getCheckerCpuPtr();
if (checker) {
checker->getDTBPtr()->allCpusCaching();
checker->getITBPtr()->allCpusCaching();
}
-#endif
}
return;
}
assert(oc->getITBPtr() && oc->getDTBPtr());
oc->getITBPtr()->flushAll();
oc->getDTBPtr()->flushAll();
-#if USE_CHECKER
- CheckerCPU *checker =
- dynamic_cast<CheckerCPU*>(oc->getCheckerCpuPtr());
+
+ // If CheckerCPU is connected, need to notify it of a flush
+ CheckerCPU *checker = oc->getCheckerCpuPtr();
if (checker) {
checker->getITBPtr()->flushAll();
checker->getDTBPtr()->flushAll();
}
-#endif
}
return;
case MISCREG_ITLBIALL:
bits(newVal, 7,0));
oc->getDTBPtr()->flushMvaAsid(mbits(newVal, 31, 12),
bits(newVal, 7,0));
-#if USE_CHECKER
- CheckerCPU *checker =
- dynamic_cast<CheckerCPU*>(oc->getCheckerCpuPtr());
+
+ CheckerCPU *checker = oc->getCheckerCpuPtr();
if (checker) {
checker->getITBPtr()->flushMvaAsid(mbits(newVal, 31, 12),
bits(newVal, 7,0));
checker->getDTBPtr()->flushMvaAsid(mbits(newVal, 31, 12),
bits(newVal, 7,0));
}
-#endif
}
return;
case MISCREG_TLBIASIDIS:
assert(oc->getITBPtr() && oc->getDTBPtr());
oc->getITBPtr()->flushAsid(bits(newVal, 7,0));
oc->getDTBPtr()->flushAsid(bits(newVal, 7,0));
-#if USE_CHECKER
- CheckerCPU *checker =
- dynamic_cast<CheckerCPU*>(oc->getCheckerCpuPtr());
+ CheckerCPU *checker = oc->getCheckerCpuPtr();
if (checker) {
checker->getITBPtr()->flushAsid(bits(newVal, 7,0));
checker->getDTBPtr()->flushAsid(bits(newVal, 7,0));
}
-#endif
}
return;
case MISCREG_TLBIMVAAIS:
assert(oc->getITBPtr() && oc->getDTBPtr());
oc->getITBPtr()->flushMva(mbits(newVal, 31,12));
oc->getDTBPtr()->flushMva(mbits(newVal, 31,12));
-#if USE_CHECKER
- CheckerCPU *checker =
- dynamic_cast<CheckerCPU*>(oc->getCheckerCpuPtr());
+
+ CheckerCPU *checker = oc->getCheckerCpuPtr();
if (checker) {
checker->getITBPtr()->flushMva(mbits(newVal, 31,12));
checker->getDTBPtr()->flushMva(mbits(newVal, 31,12));
}
-#endif
}
return;
case MISCREG_ITLBIMVA:
#include "arch/arm/tlb.hh"
#include "arch/arm/utility.hh"
#include "arch/arm/vtophys.hh"
-#include "config/use_checker.hh"
+#include "cpu/checker/cpu.hh"
#include "cpu/base.hh"
#include "cpu/thread_context.hh"
#include "mem/fs_translating_port_proxy.hh"
{
TheISA::PCState newPC = tc->pcState();
newPC.set(tc->readIntReg(ReturnAddressReg) & ~ULL(1));
-#if USE_CHECKER
- tc->pcStateNoRecord(newPC);
-#else
- tc->pcState(newPC);
-#endif
+
+ CheckerCPU *checker = tc->getCheckerCpuPtr();
+ if (checker) {
+ tc->pcStateNoRecord(newPC);
+ } else {
+ tc->pcState(newPC);
+ }
}
void
"dtb_walker_cache.mem_side"]
else:
self._cached_ports += ["itb.walker.port", "dtb.walker.port"]
+
# Checker doesn't need its own tlb caches because it does
# functional accesses only
- if buildEnv['USE_CHECKER']:
+ if self.checker != NULL:
self._cached_ports += ["checker.itb.walker.port", \
"checker.dtb.walker.port"]
self.l2cache = l2c
self.toL2Bus.master = self.l2cache.cpu_side
self._cached_ports = ['l2cache.mem_side']
+
+ def addCheckerCpu(self):
+ pass
# it's enabled. This isn't used for anything else other than StaticInst
# headers.
temp_cpu_list = env['CPU_MODELS'][:]
-
-if env['USE_CHECKER']:
- temp_cpu_list.append('CheckerCPU')
- SimObject('CheckerCPU.py')
+temp_cpu_list.append('CheckerCPU')
+SimObject('CheckerCPU.py')
# Generate header.
def gen_cpu_exec_signatures(target, source, env):
Action(gen_cpu_exec_signatures, gen_sigs_string,
varlist = temp_cpu_list))
-env.Depends('static_inst_exec_sigs.hh', Value(env['USE_CHECKER']))
env.Depends('static_inst_exec_sigs.hh', Value(env['CPU_MODELS']))
-# List of suppported CPUs by the Checker. Errors out if USE_CHECKER=True
-# and one of these are not being used.
-CheckerSupportedCPUList = ['O3CPU', 'OzoneCPU']
-
SimObject('BaseCPU.py')
SimObject('FuncUnit.py')
SimObject('ExeTracer.py')
SimObject('LegionTrace.py')
Source('legiontrace.cc')
-if env['USE_CHECKER']:
- SimObject('DummyChecker.py')
- Source('checker/cpu.cc')
- Source('dummy_checker_builder.cc')
- DebugFlag('Checker')
- checker_supports = False
- for i in CheckerSupportedCPUList:
- if i in env['CPU_MODELS']:
- checker_supports = True
- if not checker_supports:
- print "Checker only supports CPU models",
- for i in CheckerSupportedCPUList:
- print i,
- print ", please set USE_CHECKER=False or use one of those CPU models"
- Exit(1)
+SimObject('DummyChecker.py')
+Source('checker/cpu.cc')
+Source('dummy_checker_builder.cc')
+DebugFlag('Checker')
DebugFlag('Activity')
DebugFlag('Commit')
#include "base/misc.hh"
#include "base/output.hh"
#include "base/trace.hh"
-#include "config/use_checker.hh"
#include "cpu/base.hh"
+#include "cpu/checker/cpu.hh"
#include "cpu/cpuevent.hh"
#include "cpu/profile.hh"
#include "cpu/thread_context.hh"
#include "sim/sim_exit.hh"
#include "sim/system.hh"
-#if USE_CHECKER
-#include "cpu/checker/cpu.hh"
-#endif
-
// Hack
#include "sim/stat_control.hh"
peer->setPeer(new_dtb_port);
}
-#if USE_CHECKER
- Port *old_checker_itb_port, *old_checker_dtb_port;
- Port *new_checker_itb_port, *new_checker_dtb_port;
-
- CheckerCPU *oldChecker =
- dynamic_cast<CheckerCPU*>(oldTC->getCheckerCpuPtr());
- CheckerCPU *newChecker =
- dynamic_cast<CheckerCPU*>(newTC->getCheckerCpuPtr());
- old_checker_itb_port = oldChecker->getITBPtr()->getPort();
- old_checker_dtb_port = oldChecker->getDTBPtr()->getPort();
- new_checker_itb_port = newChecker->getITBPtr()->getPort();
- new_checker_dtb_port = newChecker->getDTBPtr()->getPort();
-
- // Move over any table walker ports if they exist for checker
- if (new_checker_itb_port && !new_checker_itb_port->isConnected()) {
- assert(old_checker_itb_port);
- Port *peer = old_checker_itb_port->getPeer();;
- new_checker_itb_port->setPeer(peer);
- peer->setPeer(new_checker_itb_port);
+ // Checker whether or not we have to transfer CheckerCPU
+ // objects over in the switch
+ CheckerCPU *oldChecker = oldTC->getCheckerCpuPtr();
+ CheckerCPU *newChecker = newTC->getCheckerCpuPtr();
+ if (oldChecker && newChecker) {
+ Port *old_checker_itb_port, *old_checker_dtb_port;
+ Port *new_checker_itb_port, *new_checker_dtb_port;
+
+ old_checker_itb_port = oldChecker->getITBPtr()->getPort();
+ old_checker_dtb_port = oldChecker->getDTBPtr()->getPort();
+ new_checker_itb_port = newChecker->getITBPtr()->getPort();
+ new_checker_dtb_port = newChecker->getDTBPtr()->getPort();
+
+ // Move over any table walker ports if they exist for checker
+ if (new_checker_itb_port && !new_checker_itb_port->isConnected()) {
+ assert(old_checker_itb_port);
+ Port *peer = old_checker_itb_port->getPeer();;
+ new_checker_itb_port->setPeer(peer);
+ peer->setPeer(new_checker_itb_port);
+ }
+ if (new_checker_dtb_port && !new_checker_dtb_port->isConnected()) {
+ assert(old_checker_dtb_port);
+ Port *peer = old_checker_dtb_port->getPeer();;
+ new_checker_dtb_port->setPeer(peer);
+ peer->setPeer(new_checker_dtb_port);
+ }
}
- if (new_checker_dtb_port && !new_checker_dtb_port->isConnected()) {
- assert(old_checker_dtb_port);
- Port *peer = old_checker_dtb_port->getPeer();;
- new_checker_dtb_port->setPeer(peer);
- peer->setPeer(new_checker_dtb_port);
- }
-#endif
-
}
interrupts = oldCPU->interrupts;
#include "base/fast_alloc.hh"
#include "base/trace.hh"
#include "config/the_isa.hh"
-#include "config/use_checker.hh"
+#include "cpu/checker/cpu.hh"
#include "cpu/o3/comm.hh"
#include "cpu/exetrace.hh"
#include "cpu/inst_seq.hh"
RequestPtr savedSreqLow;
RequestPtr savedSreqHigh;
-#if USE_CHECKER
// Need a copy of main request pointer to verify on writes.
RequestPtr reqToVerify;
-#endif //USE_CHECKER
/** @todo: Consider making this private. */
public:
effAddr = req->getVaddr();
effSize = size;
effAddrValid = true;
-#if USE_CHECKER
- if (reqToVerify != NULL) {
- delete reqToVerify;
+
+ if (cpu->checker) {
+ if (reqToVerify != NULL) {
+ delete reqToVerify;
+ }
+ reqToVerify = new Request(*req);
}
- reqToVerify = new Request(*req);
-#endif //USE_CHECKER
fault = cpu->read(req, sreqLow, sreqHigh, data, lqIdx);
} else {
// Commit will have to clean up whatever happened. Set this
effAddr = req->getVaddr();
effSize = size;
effAddrValid = true;
-#if USE_CHECKER
- if (reqToVerify != NULL) {
- delete reqToVerify;
+
+ if (cpu->checker) {
+ if (reqToVerify != NULL) {
+ delete reqToVerify;
+ }
+ reqToVerify = new Request(*req);
}
- reqToVerify = new Request(*req);
-#endif // USE_CHECKER
fault = cpu->write(req, sreqLow, sreqHigh, data, sqIdx);
}
#include "base/cprintf.hh"
#include "base/trace.hh"
#include "config/the_isa.hh"
-#include "config/use_checker.hh"
#include "cpu/base_dyn_inst.hh"
#include "cpu/exetrace.hh"
#include "debug/DynInst.hh"
cpu->snList.insert(seqNum);
#endif
-#if USE_CHECKER
reqToVerify = NULL;
-#endif
}
template <class Impl>
cpu->snList.erase(seqNum);
#endif
-#if USE_CHECKER
if (reqToVerify)
delete reqToVerify;
-#endif // USE_CHECKER
}
#ifdef DEBUG
#include "cpu/static_inst.hh"
#include "cpu/thread_context.hh"
#include "params/CheckerCPU.hh"
+#include "sim/full_system.hh"
#include "sim/tlb.hh"
using namespace std;
dtb = p->dtb;
systemPtr = NULL;
workload = p->workload;
- // XXX: This is a hack to get this to work some
- thread = new SimpleThread(this, /* thread_num */ 0,
- workload.size() ? workload[0] : NULL, itb, dtb);
-
- tc = thread->getTC();
- threadContexts.push_back(tc);
+ thread = NULL;
updateOnError = true;
}
{
systemPtr = system;
- thread = new SimpleThread(this, 0, systemPtr, itb, dtb, false);
+ if (FullSystem) {
+ thread = new SimpleThread(this, 0, systemPtr, itb, dtb, false);
+ } else {
+ thread = new SimpleThread(this, 0, systemPtr,
+ workload.size() ? workload[0] : NULL,
+ itb, dtb);
+ }
tc = thread->getTC();
threadContexts.push_back(tc);
- delete thread->kernelStats;
thread->kernelStats = NULL;
+ // Thread should never be null after this
+ assert(thread != NULL);
}
void
-CheckerCPU::setIcachePort(Port *icache_port)
+CheckerCPU::setIcachePort(CpuPort *icache_port)
{
icachePort = icache_port;
}
void
-CheckerCPU::setDcachePort(Port *dcache_port)
+CheckerCPU::setDcachePort(CpuPort *dcache_port)
{
dcachePort = dcache_port;
}
// Need to account for multiple accesses like the Atomic and TimingSimple
while (1) {
memReq = new Request();
- memReq->setVirt(0, addr, size, flags, thread->pcState().instAddr());
+ memReq->setVirt(0, addr, size, flags, masterId, thread->pcState().instAddr());
// translate to physical address
fault = dtb->translateFunctional(memReq, tc, BaseTLB::Read);
System *systemPtr;
- void setIcachePort(Port *icache_port);
+ void setIcachePort(CpuPort *icache_port);
- Port *icachePort;
+ CpuPort *icachePort;
- void setDcachePort(Port *dcache_port);
+ void setDcachePort(CpuPort *dcache_port);
- Port *dcachePort;
+ CpuPort *dcachePort;
+
+ CpuPort &getDataPort()
+ {
+ panic("Not supported on checker!");
+ return *dcachePort;
+ }
+
+ CpuPort &getInstPort()
+ {
+ panic("Not supported on checker!");
+ return *icachePort;
+ }
virtual Port *getPort(const std::string &name, int idx)
{
TheISA::TLB* getITBPtr() { return itb; }
TheISA::TLB* getDTBPtr() { return dtb; }
- virtual Counter totalInstructions() const
+ virtual Counter totalInsts() const
+ {
+ return 0;
+ }
+
+ virtual Counter totalOps() const
{
return 0;
}
memReq = new Request(unverifiedInst->threadNumber, fetch_PC,
sizeof(MachInst),
0,
+ masterId,
fetch_PC, thread->contextId(),
unverifiedInst->threadNumber);
memReq->setVirt(0, fetch_PC, sizeof(MachInst),
// Take any faults here
if (fault != NoFault) {
- fault->invoke(tc, curStaticInst);
- willChangePC = true;
- newPCState = thread->pcState();
- DPRINTF(Checker, "Fault, PC is now %s\n", newPCState);
- curMacroStaticInst = StaticInst::nullStaticInstPtr;
+ if (FullSystem) {
+ fault->invoke(tc, curStaticInst);
+ willChangePC = true;
+ newPCState = thread->pcState();
+ DPRINTF(Checker, "Fault, PC is now %s\n", newPCState);
+ curMacroStaticInst = StaticInst::nullStaticInstPtr;
+ }
} else {
advancePC(fault);
}
TheISA::TLB *getDTBPtr() { return actualTC->getDTBPtr(); }
- BaseCPU *getCheckerCpuPtr() { return checkerTC->getCpuPtr(); }
+ CheckerCPU *getCheckerCpuPtr()
+ {
+ return checkerCPU;
+ }
Decoder *getDecoderPtr() { return actualTC->getDecoderPtr(); }
FSTranslatingPortProxy &getVirtProxy()
{ return actualTC->getVirtProxy(); }
- //XXX: How does this work now?
void initMemProxies(ThreadContext *tc)
{ actualTC->initMemProxies(tc); }
temp = max_insts_all_threads;
temp = max_loads_any_thread;
temp = max_loads_all_threads;
+ temp++;
Tick temp2 = progress_interval;
params->progress_interval = 0;
temp2++;
from m5.proxy import *
from BaseCPU import BaseCPU
from FUPool import *
-
-if buildEnv['USE_CHECKER']:
- from O3Checker import O3Checker
+from O3Checker import O3Checker
class DerivO3CPU(BaseCPU):
type = 'DerivO3CPU'
activity = Param.Unsigned(0, "Initial count")
- if buildEnv['USE_CHECKER']:
- # FIXME: Shouldn't need to derefernce Parent.workload
- # Somewhere in the param parsing code
- # src/python/m5/params.py is and error that
- # has trouble converting the workload parameter properly.
- checker = Param.BaseCPU(O3Checker(workload=Parent.workload[0],
- exitOnError=False,
- updateOnError=True,
- warnOnlyOnLoadError=True),
- "checker")
- checker.itb = Parent.itb
- checker.dtb = Parent.dtb
-
cachePorts = Param.Unsigned(200, "Cache Ports")
decodeToFetchDelay = Param.Unsigned(1, "Decode to fetch delay")
needsTSO = Param.Bool(buildEnv['TARGET_ISA'] == 'x86',
"Enable TSO Memory model")
+
+ def addCheckerCpu(self):
+ if buildEnv['TARGET_ISA'] in ['arm']:
+ from ArmTLB import ArmTLB
+
+ self.checker = O3Checker(workload=self.workload,
+ exitOnError=False,
+ updateOnError=True,
+ warnOnlyOnLoadError=True)
+ self.checker.itb = ArmTLB(size = self.itb.size)
+ self.checker.dtb = ArmTLB(size = self.dtb.size)
+
+ else:
+ print "ERROR: Checker only supported under ARM ISA!"
+ exit(1)
'IQ', 'ROB', 'FreeList', 'LSQ', 'LSQUnit', 'StoreSet', 'MemDepUnit',
'DynInst', 'O3CPU', 'Activity', 'Scoreboard', 'Writeback' ])
- if env['USE_CHECKER']:
- SimObject('O3Checker.py')
- Source('checker_builder.cc')
+ SimObject('O3Checker.py')
+ Source('checker_builder.cc')
temp = max_insts_all_threads;
temp = max_loads_any_thread;
temp = max_loads_all_threads;
+ temp++;
Tick temp2 = progress_interval;
params->progress_interval = 0;
temp2++;
#include "base/loader/symtab.hh"
#include "base/cp_annotate.hh"
#include "config/the_isa.hh"
-#include "config/use_checker.hh"
+#include "cpu/checker/cpu.hh"
#include "cpu/o3/commit.hh"
#include "cpu/o3/thread_state.hh"
#include "cpu/base.hh"
#include "sim/faults.hh"
#include "sim/full_system.hh"
-#if USE_CHECKER
-#include "cpu/checker/cpu.hh"
-#endif
-
using namespace std;
template <class Impl>
assert(!thread[0]->inSyscall);
thread[0]->inSyscall = true;
-#if USE_CHECKER
if (cpu->checker) {
cpu->checker->handlePendingInt();
}
-#endif
// CPU will handle interrupt.
cpu->processInterrupts(interrupt);
head_inst->setCompleted();
}
-#if USE_CHECKER
// Use checker prior to updating anything due to traps or PC
// based events.
if (cpu->checker) {
cpu->checker->verify(head_inst);
}
-#endif
if (inst_fault != NoFault) {
DPRINTF(Commit, "Inst [sn:%lli] PC %s has a fault\n",
head_inst->setCompleted();
-#if USE_CHECKER
if (cpu->checker) {
// Need to check the instruction before its fault is processed
cpu->checker->verify(head_inst);
}
-#endif
assert(!thread[tid]->inSyscall);
#include "arch/kernel_stats.hh"
#include "config/the_isa.hh"
-#include "config/use_checker.hh"
+#include "cpu/checker/cpu.hh"
+#include "cpu/checker/thread_context.hh"
#include "cpu/o3/cpu.hh"
#include "cpu/o3/isa_specific.hh"
#include "cpu/o3/thread_context.hh"
#include "sim/stat_control.hh"
#include "sim/system.hh"
-#if USE_CHECKER
-#include "cpu/checker/cpu.hh"
-#include "cpu/checker/thread_context.hh"
-#endif
-
#if THE_ISA == ALPHA_ISA
#include "arch/alpha/osfpal.hh"
#include "debug/Activity.hh"
_status = Idle;
}
-#if USE_CHECKER
if (params->checker) {
BaseCPU *temp_checker = params->checker;
checker = dynamic_cast<Checker<Impl> *>(temp_checker);
} else {
checker = NULL;
}
-#endif // USE_CHECKER
if (!FullSystem) {
thread.resize(numThreads);
// If we're using a checker, then the TC should be the
// CheckerThreadContext.
-#if USE_CHECKER
if (params->checker) {
tc = new CheckerThreadContext<O3ThreadContext<Impl> >(
o3_tc, this->checker);
}
-#endif
o3_tc->cpu = (typename Impl::O3CPU *)(this);
assert(o3_tc->cpu);
}
_status = SwitchedOut;
-#if USE_CHECKER
+
if (checker)
checker->switchOut();
-#endif
+
if (tickEvent.scheduled())
tickEvent.squash();
}
#include "arch/types.hh"
#include "base/statistics.hh"
#include "config/the_isa.hh"
-#include "config/use_checker.hh"
#include "cpu/o3/comm.hh"
#include "cpu/o3/cpu_policy.hh"
#include "cpu/o3/scoreboard.hh"
/** The global sequence number counter. */
InstSeqNum globalSeqNum;//[Impl::MaxThreads];
-#if USE_CHECKER
/** Pointer to the checker, which can dynamically verify
* instruction results at run time. This can be set to NULL if it
* is not being used.
*/
Checker<Impl> *checker;
-#endif
/** Pointer to the system. */
System *system;
#include <string>
-#include "config/use_checker.hh"
#include "cpu/o3/cpu.hh"
#include "cpu/o3/impl.hh"
#include "params/DerivO3CPU.hh"
*/
#include "base/cp_annotate.hh"
-#include "config/use_checker.hh"
#include "cpu/o3/dyn_inst.hh"
#include "sim/full_system.hh"
bool in_syscall = this->thread->inSyscall;
this->thread->inSyscall = true;
-#if USE_CHECKER
- if (this->isStoreConditional()) {
- this->reqToVerify->setExtraData(pkt->req->getExtraData());
+ if (this->cpu->checker) {
+ if (this->isStoreConditional()) {
+ this->reqToVerify->setExtraData(pkt->req->getExtraData());
+ }
}
-#endif
+
this->fault = this->staticInst->completeAcc(pkt, this, this->traceData);
this->thread->inSyscall = in_syscall;
#include "arch/vtophys.hh"
#include "base/types.hh"
#include "config/the_isa.hh"
-#include "config/use_checker.hh"
#include "cpu/base.hh"
+//#include "cpu/checker/cpu.hh"
#include "cpu/o3/fetch.hh"
#include "cpu/exetrace.hh"
#include "debug/Activity.hh"
#include "sim/full_system.hh"
#include "sim/system.hh"
-#if USE_CHECKER
-#include "cpu/checker/cpu.hh"
-#endif // USE_CHECKER
-
using namespace std;
template<class Impl>
#include "arch/utility.hh"
#include "config/the_isa.hh"
-#include "config/use_checker.hh"
+#include "cpu/checker/cpu.hh"
#include "cpu/o3/fu_pool.hh"
#include "cpu/o3/iew.hh"
#include "cpu/timebuf.hh"
#include "debug/IEW.hh"
#include "params/DerivO3CPU.hh"
-#if USE_CHECKER
-#include "cpu/checker/cpu.hh"
-#endif // USE_CHECKER
-
using namespace std;
template<class Impl>
ldstQueue.numFreeEntries(tid);
}
-// Initialize the checker's dcache port here
-#if USE_CHECKER
+ // Initialize the checker's dcache port here
if (cpu->checker) {
cpu->checker->setDcachePort(&cpu->getDataPort());
- }
-#endif
+ }
cpu->activateStage(O3CPU::IEWIdx);
}
#include "arch/locked_mem.hh"
#include "base/str.hh"
#include "config/the_isa.hh"
+#include "cpu/checker/cpu.hh"
#include "cpu/o3/lsq.hh"
#include "cpu/o3/lsq_unit.hh"
#include "debug/Activity.hh"
#include "mem/packet.hh"
#include "mem/request.hh"
-#if USE_CHECKER
-#include "cpu/checker/cpu.hh"
-#endif
-
template<class Impl>
LSQUnit<Impl>::WritebackEvent::WritebackEvent(DynInstPtr &_inst, PacketPtr _pkt,
LSQUnit *lsq_ptr)
inst->seqNum);
WritebackEvent *wb = new WritebackEvent(inst, data_pkt, this);
cpu->schedule(wb, curTick() + 1);
-#if USE_CHECKER
- // Make sure to set the LLSC data for verification
- inst->reqToVerify->setExtraData(0);
- inst->completeAcc(data_pkt);
-#endif
+ if (cpu->checker) {
+ // Make sure to set the LLSC data for verification
+ // if checker is loaded
+ inst->reqToVerify->setExtraData(0);
+ inst->completeAcc(data_pkt);
+ }
completeStore(storeWBIdx);
incrStIdx(storeWBIdx);
continue;
// only works so long as the checker doesn't try to
// verify the value in memory for stores.
storeQueue[storeWBIdx].inst->setCompleted();
-#if USE_CHECKER
+
if (cpu->checker) {
cpu->checker->verify(storeQueue[storeWBIdx].inst);
}
-#endif
}
if (needsTSO) {
// Tell the checker we've completed this instruction. Some stores
// may get reported twice to the checker, but the checker can
// handle that case.
-#if USE_CHECKER
if (cpu->checker) {
cpu->checker->verify(storeQueue[store_idx].inst);
}
-#endif
}
template <class Impl>
#define __CPU_O3_THREAD_CONTEXT_HH__
#include "config/the_isa.hh"
-#include "config/use_checker.hh"
#include "cpu/o3/isa_specific.hh"
#include "cpu/thread_context.hh"
/** Returns a pointer to the DTB. */
TheISA::TLB *getDTBPtr() { return cpu->dtb; }
-#if USE_CHECKER
- BaseCPU *getCheckerCpuPtr() { return NULL; }
-#endif
+ CheckerCPU *getCheckerCpuPtr() { return NULL; }
Decoder *getDecoderPtr() { return &cpu->fetch.decoder; }
/** Sets this thread's PC state. */
virtual void pcState(const TheISA::PCState &val);
-#if USE_CHECKER
virtual void pcStateNoRecord(const TheISA::PCState &val);
-#endif
/** Reads this thread's PC. */
virtual Addr instAddr()
#include "arch/kernel_stats.hh"
#include "arch/registers.hh"
#include "config/the_isa.hh"
-#include "config/use_checker.hh"
#include "cpu/o3/thread_context.hh"
#include "cpu/quiesce_event.hh"
#include "debug/O3CPU.hh"
}
}
-#if USE_CHECKER
template <class Impl>
void
O3ThreadContext<Impl>::pcStateNoRecord(const TheISA::PCState &val)
cpu->squashFromTC(thread->threadId());
}
}
-#endif
template <class Impl>
int
from m5.defines import buildEnv
from m5.params import *
from BaseCPU import BaseCPU
-
-if buildEnv['USE_CHECKER']:
- from OzoneChecker import OzoneChecker
+from OzoneChecker import OzoneChecker
class DerivOzoneCPU(BaseCPU):
type = 'DerivOzoneCPU'
numThreads = Param.Unsigned("number of HW thread contexts")
- if buildEnv['USE_CHECKER']:
- checker = Param.BaseCPU("Checker CPU")
-
icache_port = Port("Instruction Port")
dcache_port = Port("Data Port")
function_trace = Param.Bool(False, "Enable function trace")
function_trace_start = Param.Tick(0, "Cycle to start function trace")
+
+ # If the CheckerCPU is brought back to useability in the OzoneCPU, create a
+ # function here called addCheckerCpu() to create a non-NULL Checker and
+ # connect its TLBs (if needed)
CompoundFlag('OzoneCPUAll', [ 'BE', 'FE', 'IBE', 'OzoneLSQ', 'OzoneCPU' ])
- if env['USE_CHECKER']:
- SimObject('OzoneChecker.py')
- Source('checker_builder.cc')
+ SimObject('OzoneChecker.py')
+ Source('checker_builder.cc')
#include "base/callback.hh"
#include "base/trace.hh"
#include "config/the_isa.hh"
-#include "config/use_checker.hh"
+#include "cpu/checker/thread_context.hh"
#include "cpu/ozone/cpu.hh"
#include "cpu/base.hh"
#include "cpu/exetrace.hh"
#include "sim/stats.hh"
#include "sim/system.hh"
-#if USE_CHECKER
-#include "cpu/checker/thread_context.hh"
-#endif
-
using namespace TheISA;
template <class Impl>
_status = Idle;
if (p->checker) {
-#if USE_CHECKER
BaseCPU *temp_checker = p->checker;
checker = dynamic_cast<Checker<DynInstPtr> *>(temp_checker);
checker->setSystem(p->system);
checkerTC = new CheckerThreadContext<OzoneTC>(&ozoneTC, checker);
thread.tc = checkerTC;
tc = checkerTC;
-#else
- panic("Checker enabled but not compiled in!");
-#endif
} else {
// If checker is not being used, then the xcProxy points
// directly to the CPU's ExecContext.
if (++switchCount == 2) {
backEnd->doSwitchOut();
frontEnd->doSwitchOut();
-#if USE_CHECKER
+
if (checker)
checker->switchOut();
-#endif
_status = SwitchedOut;
#ifndef NDEBUG
#include "arch/utility.hh"
#include "base/statistics.hh"
#include "config/the_isa.hh"
-#include "config/use_checker.hh"
+#include "cpu/checker/cpu.hh"
#include "cpu/ozone/front_end.hh"
#include "cpu/exetrace.hh"
#include "cpu/thread_context.hh"
#include "mem/request.hh"
#include "sim/faults.hh"
-#if USE_CHECKER
-#include "cpu/checker/cpu.hh"
-#endif
-
using namespace TheISA;
template<class Impl>
icachePort.setName(this->name() + "-iport");
-#if USE_CHECKER
if (cpu->checker) {
cpu->checker->setIcachePort(&icachePort);
}
-#endif
}
template <class Impl>
*/
#include "config/the_isa.hh"
-#include "config/use_checker.hh"
+#include "cpu/checker/cpu.hh"
#include "cpu/ozone/lw_back_end.hh"
#include "cpu/op_class.hh"
-#if USE_CHECKER
-#include "cpu/checker/cpu.hh"
-#endif
-
template <class Impl>
void
LWBackEnd<Impl>::generateTrapEvent(Tick latency)
// Use checker prior to updating anything due to traps or PC
// based events.
-#if USE_CHECKER
if (checker) {
checker->verify(inst);
}
-#endif
if (inst_fault != NoFault) {
DPRINTF(BE, "Inst [sn:%lli] PC %#x has a fault\n",
DPRINTF(BE, "Will wait until instruction is head of commit group.\n");
return false;
}
-#if USE_CHECKER
else if (checker && inst->isStore()) {
checker->verify(inst);
}
-#endif
handleFault(inst_fault);
return false;
#include "base/str.hh"
#include "config/the_isa.hh"
-#include "config/use_checker.hh"
#include "cpu/checker/cpu.hh"
#include "cpu/ozone/lw_lsq.hh"
#include "sim/fault_fwd.hh"
cpu = cpu_ptr;
dcachePort.setName(this->name() + "-dport");
-#if USE_CHECKER
if (cpu->checker) {
cpu->checker->setDcachePort(&dcachePort);
}
-#endif
}
template<class Impl>
// only works so long as the checker doesn't try to
// verify the value in memory for stores.
inst->setCompleted();
-#if USE_CHECKER
if (cpu->checker) {
cpu->checker->verify(inst);
}
-#endif
}
}
--stores;
inst->setCompleted();
-#if USE_CHECKER
if (cpu->checker) {
cpu->checker->verify(inst);
}
-#endif
}
template <class Impl>
from m5.defines import buildEnv
from m5.params import *
from BaseCPU import BaseCPU
-
-if buildEnv['USE_CHECKER']:
- from DummyChecker import DummyChecker
+from DummyChecker import DummyChecker
class BaseSimpleCPU(BaseCPU):
type = 'BaseSimpleCPU'
abstract = True
- if buildEnv['USE_CHECKER']:
- checker = Param.BaseCPU(DummyChecker(), "checker")
- checker.itb = BaseCPU.itb
- checker.dtb = BaseCPU.dtb
+ def addCheckerCpu(self):
+ if buildEnv['TARGET_ISA'] in ['arm']:
+ from ArmTLB import ArmTLB
+
+ self.checker = DummyChecker(workload = self.workload)
+ self.checker.itb = ArmTLB(size = self.itb.size)
+ self.checker.dtb = ArmTLB(size = self.dtb.size)
+ else:
+ print "ERROR: Checker only supported under ARM ISA!"
+ exit(1)
#include "base/trace.hh"
#include "base/types.hh"
#include "config/the_isa.hh"
-#include "config/use_checker.hh"
#include "cpu/simple/base.hh"
#include "cpu/base.hh"
+#include "cpu/checker/cpu.hh"
+#include "cpu/checker/thread_context.hh"
#include "cpu/exetrace.hh"
#include "cpu/profile.hh"
#include "cpu/simple_thread.hh"
#include "sim/stats.hh"
#include "sim/system.hh"
-#if USE_CHECKER
-#include "cpu/checker/cpu.hh"
-#include "cpu/checker/thread_context.hh"
-#endif
-
using namespace std;
using namespace TheISA;
tc = thread->getTC();
-#if USE_CHECKER
if (p->checker) {
BaseCPU *temp_checker = p->checker;
checker = dynamic_cast<CheckerCPU *>(temp_checker);
} else {
checker = NULL;
}
-#endif
numInst = 0;
startNumInst = 0;
#include "arch/predecoder.hh"
#include "base/statistics.hh"
#include "config/the_isa.hh"
-#include "config/use_checker.hh"
#include "cpu/base.hh"
+#include "cpu/checker/cpu.hh"
#include "cpu/decode.hh"
#include "cpu/pc_event.hh"
#include "cpu/simple_thread.hh"
#include "sim/full_system.hh"
#include "sim/system.hh"
-#if USE_CHECKER
-#include "cpu/checker/cpu.hh"
-#endif
-
// forward declarations
class Checkpoint;
class Process;
*/
ThreadContext *tc;
-#if USE_CHECKER
CheckerCPU *checker;
-#endif
+
protected:
enum Status {
#include "arch/types.hh"
#include "base/types.hh"
#include "config/the_isa.hh"
-#include "config/use_checker.hh"
#include "cpu/decode.hh"
#include "cpu/thread_context.hh"
#include "cpu/thread_state.hh"
#include "sim/system.hh"
class BaseCPU;
-
+class CheckerCPU;
class FunctionProfile;
class ProfileNode;
TheISA::TLB *getDTBPtr() { return dtb; }
-#if USE_CHECKER
- BaseCPU *getCheckerCpuPtr() { return NULL; }
-#endif
+ CheckerCPU *getCheckerCpuPtr() { return NULL; }
Decoder *getDecoderPtr() { return &decoder; }
_pcState = val;
}
-#if USE_CHECKER
void
pcStateNoRecord(const TheISA::PCState &val)
{
_pcState = val;
}
-#endif
Addr
instAddr()
#include "arch/types.hh"
#include "base/types.hh"
#include "config/the_isa.hh"
-#include "config/use_checker.hh"
// @todo: Figure out a more architecture independent way to obtain the ITB and
// DTB pointers.
class TLB;
}
class BaseCPU;
+class CheckerCPU;
class Checkpoint;
class Decoder;
class EndQuiesceEvent;
virtual TheISA::TLB *getDTBPtr() = 0;
-#if USE_CHECKER
- virtual BaseCPU *getCheckerCpuPtr() = 0;
-#endif
+ virtual CheckerCPU *getCheckerCpuPtr() = 0;
virtual Decoder *getDecoderPtr() = 0;
virtual void pcState(const TheISA::PCState &val) = 0;
-#if USE_CHECKER
virtual void pcStateNoRecord(const TheISA::PCState &val) = 0;
-#endif
virtual Addr instAddr() = 0;
TheISA::TLB *getDTBPtr() { return actualTC->getDTBPtr(); }
-#if USE_CHECKER
- BaseCPU *getCheckerCpuPtr() { return actualTC->getCheckerCpuPtr(); }
-#endif
+ CheckerCPU *getCheckerCpuPtr() { return actualTC->getCheckerCpuPtr(); }
Decoder *getDecoderPtr() { return actualTC->getDecoderPtr(); }
void pcState(const TheISA::PCState &val) { actualTC->pcState(val); }
-#if USE_CHECKER
void pcStateNoRecord(const TheISA::PCState &val) { actualTC->pcState(val); }
-#endif
Addr instAddr() { return actualTC->instAddr(); }
Addr nextInstAddr() { return actualTC->nextInstAddr(); }
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