i965: Add definitions for Sandybridge DP write/read messages.

diff --git a/src/mesa/drivers/dri/i965/brw_defines.h b/src/mesa/drivers/dri/i965/brw_defines.h
index 39bf5b63fc2a6cdd4962e4c5bd6c8a2bce6c7b83..dba500c56217c6d7d5e13b425b06a466797c7849 100644 (file)
--- a/src/mesa/drivers/dri/i965/brw_defines.h
+++ b/src/mesa/drivers/dri/i965/brw_defines.h
@@ -501,6 +501,10 @@
 #define BRW_MASK_ENABLE   0
 #define BRW_MASK_DISABLE  1
 
+/* Sandybridge is WECtrl (Write enable control) */
+#define BRW_WE_NORMAL          0
+#define BRW_WE_KILL_PRED       1
+
 #define BRW_OPCODE_MOV        1
 #define BRW_OPCODE_SEL        2
 #define BRW_OPCODE_NOT        4
@@ -646,13 +650,14 @@
 #define BRW_POLYGON_FACING_BACK       1
 
 #define BRW_MESSAGE_TARGET_NULL               0
-#define BRW_MESSAGE_TARGET_MATH               1
+#define BRW_MESSAGE_TARGET_MATH               1 /* reserved on GEN6 */
 #define BRW_MESSAGE_TARGET_SAMPLER            2
 #define BRW_MESSAGE_TARGET_GATEWAY            3
-#define BRW_MESSAGE_TARGET_DATAPORT_READ      4
-#define BRW_MESSAGE_TARGET_DATAPORT_WRITE     5
+#define BRW_MESSAGE_TARGET_DATAPORT_READ      4 /* sampler cache on GEN6 */
+#define BRW_MESSAGE_TARGET_DATAPORT_WRITE     5 /* render cache on Gen6 */
 #define BRW_MESSAGE_TARGET_URB                6
 #define BRW_MESSAGE_TARGET_THREAD_SPAWNER     7
+#define BRW_MESSAGE_TARGET_CONST_CACHE       9 /* GEN6 */
 
 #define BRW_SAMPLER_RETURN_FORMAT_FLOAT32     0
 #define BRW_SAMPLER_RETURN_FORMAT_UINT32      2
@@ -699,9 +704,13 @@
 #define BRW_DATAPORT_DWORD_SCATTERED_BLOCK_16DWORDS  3
 
 #define BRW_DATAPORT_READ_MESSAGE_OWORD_BLOCK_READ          0
-#define BRW_DATAPORT_READ_MESSAGE_OWORD_DUAL_BLOCK_READ     1
-#define BRW_DATAPORT_READ_MESSAGE_DWORD_BLOCK_READ          2
-#define BRW_DATAPORT_READ_MESSAGE_DWORD_SCATTERED_READ      3
+/* GEN6 */
+#define BRW_DATAPORT_READ_MESSAGE_RENDER_UNORM_READ        1
+#define BRW_DATAPORT_READ_MESSAGE_OWORD_DUAL_BLOCK_READ     2
+#define BRW_DATAPORT_READ_MESSAGE_DWORD_BLOCK_READ          4
+/* GEN6 */
+#define BRW_DATAPORT_READ_MESSAGE_OWORD_UNALIGN_BLOCK_READ  5
+#define BRW_DATAPORT_READ_MESSAGE_DWORD_SCATTERED_READ      6
 
 #define BRW_DATAPORT_READ_TARGET_DATA_CACHE      0
 #define BRW_DATAPORT_READ_TARGET_RENDER_CACHE    1
@@ -721,6 +730,16 @@
 #define BRW_DATAPORT_WRITE_MESSAGE_STREAMED_VERTEX_BUFFER_WRITE     5
 #define BRW_DATAPORT_WRITE_MESSAGE_FLUSH_RENDER_CACHE               7
 
+/* GEN6 */
+#define BRW_DATAPORT_WRITE_MESSAGE_DWORD_ATOMIC_WRITE_GEN6             7
+#define BRW_DATAPORT_WRITE_MESSAGE_OWORD_BLOCK_WRITE_GEN6              8
+#define BRW_DATAPORT_WRITE_MESSAGE_OWORD_DUAL_BLOCK_WRITE_GEN6         9
+#define BRW_DATAPORT_WRITE_MESSAGE_MEDIA_BLOCK_WRITE_GEN6              10
+#define BRW_DATAPORT_WRITE_MESSAGE_DWORLD_SCATTERED_WRITE_GEN6         11
+#define BRW_DATAPORT_WRITE_MESSAGE_RENDER_TARGET_WRITE_GEN6            12
+#define BRW_DATAPORT_WRITE_MESSAGE_STREAMED_VB_WRITE_GEN6              13
+#define BRW_DATAPORT_WRITE_MESSAGE_RENDER_TARGET_UNORM_WRITE_GEN6      14
+
 #define BRW_MATH_FUNCTION_INV                              1
 #define BRW_MATH_FUNCTION_LOG                              2
 #define BRW_MATH_FUNCTION_EXP                              3

diff --git a/src/mesa/drivers/dri/i965/brw_structs.h b/src/mesa/drivers/dri/i965/brw_structs.h
index 2a7fa5b69978a234f7a59b96f405da6782bf11cf..205d1b90fd7674336491d39e1f46e394ee30a269 100644 (file)
--- a/src/mesa/drivers/dri/i965/brw_structs.h
+++ b/src/mesa/drivers/dri/i965/brw_structs.h
@@ -1657,6 +1657,34 @@ struct brw_instruction
         GLuint end_of_thread:1;
       } dp_write_gen5;
 
+      /* Sandybridge DP for sample cache, constant cache, render cache */
+      struct {
+        GLuint binding_table_index:8;
+        GLuint msg_control:5;
+        GLuint msg_type:3;
+        GLuint pad0:3;
+        GLuint header_present:1;
+        GLuint response_length:5;
+        GLuint msg_length:4;
+        GLuint pad1:2;
+        GLuint end_of_thread:1;
+      } dp_sampler_const_cache;
+
+      struct {
+        GLuint binding_table_index:8;
+        GLuint msg_control:3;
+        GLuint slot_group_select:1;
+        GLuint pixel_scoreboard_clear:1;
+        GLuint msg_type:4;
+        GLuint send_commit_msg:1;
+        GLuint pad0:1;
+        GLuint header_present:1;
+        GLuint response_length:5;
+        GLuint msg_length:4;
+        GLuint pad1:2;
+        GLuint end_of_thread:1;
+      } dp_render_cache;
+
       struct {
         GLuint pad:16;
         GLuint response_length:4;