2002-08-19 Elena Zannoni <ezannoni@redhat.com>

        From matthew green  <mrg@redhat.com>

        * ppc.h (PPC_OPCODE_SPE): New opcode flag for Powerpc e500
        instructions.
        (PPC_OPCODE_ISEL, PPC_OPCODE_BRLOCK, PPC_OPCODE_PMR,
        PPC_OPCODE_CACHELCK, PPC_OPCODE_RFMCI): New opcode flags for the
        e500x2 Integer select, branch locking, performance monitor,
        cache locking and machine check APUs, respectively.
        (PPC_OPCODE_EFS): New opcode type for efs* instructions.
        (PPC_OPCODE_CLASSIC): New opcode type for Classic PowerPC instructions.

diff --git a/include/opcode/ChangeLog b/include/opcode/ChangeLog
index f3205b5f0e65ec84f2fed4b9432b86812fb37e87..b950eefc36829678f7ce28639e5f9a5e1f267ee5 100644 (file)
--- a/include/opcode/ChangeLog
+++ b/include/opcode/ChangeLog
@@ -1,3 +1,16 @@
+2002-08-19  Elena Zannoni <ezannoni@redhat.com>
+ 
+        From matthew green  <mrg@redhat.com>
+
+        * ppc.h (PPC_OPCODE_SPE): New opcode flag for Powerpc e500
+       instructions.
+        (PPC_OPCODE_ISEL, PPC_OPCODE_BRLOCK, PPC_OPCODE_PMR,
+       PPC_OPCODE_CACHELCK, PPC_OPCODE_RFMCI): New opcode flags for the
+       e500x2 Integer select, branch locking, performance monitor,
+       cache locking and machine check APUs, respectively.
+       (PPC_OPCODE_EFS): New opcode type for efs* instructions.
+       (PPC_OPCODE_CLASSIC): New opcode type for Classic PowerPC instructions.
+
 2002-08-13  Stephane Carrez  <stcarrez@nerim.fr>
 
        * m68hc11.h (M6812_OP_PAGE): Define to identify call operand.

diff --git a/include/opcode/ppc.h b/include/opcode/ppc.h
index f7db66f63a8b455bc54f1e0c2f3912149c6b07a0..ffd313acd527486c99c2c01b15d1f86a1def04ae 100644 (file)
--- a/include/opcode/ppc.h
+++ b/include/opcode/ppc.h
@@ -107,6 +107,30 @@ extern const int powerpc_num_opcodes;
 /* Opcode isn't supported by Power4 architecture.  */
 #define PPC_OPCODE_NOPOWER4 (040000)
 
+/* Opcode is only supported by POWERPC Classic architecture.  */
+#define PPC_OPCODE_CLASSIC (0100000)
+
+/* Opcode is only supported by e500x2 Core.  */
+#define PPC_OPCODE_SPE     (0200000)
+
+/* Opcode is supported by e500x2 Integer select APU.  */
+#define PPC_OPCODE_ISEL     (0400000)
+
+/* Opcode is an e500 SPE floating point instruction.  */
+#define PPC_OPCODE_EFS      (01000000)
+
+/* Opcode is supported by branch locking APU.  */
+#define PPC_OPCODE_BRLOCK   (02000000)
+
+/* Opcode is supported by performance monitor APU.  */
+#define PPC_OPCODE_PMR      (04000000)
+
+/* Opcode is supported by cache locking APU.  */
+#define PPC_OPCODE_CACHELCK (010000000)
+
+/* Opcode is supported by machine check APU.  */
+#define PPC_OPCODE_RFMCI    (020000000)
+
 /* A macro to extract the major opcode from an instruction.  */
 #define PPC_OP(i) (((i) >> 26) & 0x3f)
 \f