re PR target/15084 (-O/-O2 generate wrong code on structure modification)

2004-05-17  H.J. Lu  <hongjiu.lu@intel.com>

	PR target/15084
	* config/i386/i386.md (*movsi_insv_1_rex64): Changed to DImode
	and renamed to movdi_insv_1_rex64.
	(insv): Support SImode for 32bit and DImode for 64bit.

From-SVN: r81936

diff --git a/gcc/ChangeLog b/gcc/ChangeLog
index 61bca60e7d387b64f6e8fcd21b530f441e5e660a..694bb5cda3d5e5c61e509cba11e03cdec045ae31 100644 (file)
--- a/gcc/ChangeLog
+++ b/gcc/ChangeLog
@@ -1,3 +1,10 @@
+2004-05-17  H.J. Lu  <hongjiu.lu@intel.com>
+
+       PR target/15084
+       * config/i386/i386.md (*movsi_insv_1_rex64): Changed to DImode
+       and renamed to movdi_insv_1_rex64.
+       (insv): Support SImode for 32bit and DImode for 64bit.
+
 2004-05-17  Richard Sandiford  <rsandifo@redhat.com>
 
        * config/mips/mips.h (MASK_DEBUG_G, TARGET_DEBUG_G_MODE): Delete.

diff --git a/gcc/config/i386/i386.md b/gcc/config/i386/i386.md
index b1366799ba301c665dfdd81e4b19a346a90fa584..270168ff75b9421df6c714cf0ef0a6bbc05789f6 100644 (file)
--- a/gcc/config/i386/i386.md
+++ b/gcc/config/i386/i386.md
@@ -1775,11 +1775,11 @@
   [(set_attr "type" "imov")
    (set_attr "mode" "QI")])
 
-(define_insn "*movsi_insv_1_rex64"
-  [(set (zero_extract:SI (match_operand 0 "ext_register_operand" "+Q")
+(define_insn "movdi_insv_1_rex64"
+  [(set (zero_extract:DI (match_operand 0 "ext_register_operand" "+Q")
                         (const_int 8)
                         (const_int 8))
-       (match_operand:SI 1 "nonmemory_operand" "Qn"))]
+       (match_operand:DI 1 "nonmemory_operand" "Qn"))]
   "TARGET_64BIT"
   "mov{b}\t{%b1, %h0|%h0, %b1}"
   [(set_attr "type" "imov")
@@ -12614,10 +12614,10 @@
 })
 
 (define_expand "insv"
-  [(set (zero_extract:SI (match_operand 0 "ext_register_operand" "")
-                        (match_operand:SI 1 "immediate_operand" "")
-                        (match_operand:SI 2 "immediate_operand" ""))
-        (match_operand:SI 3 "register_operand" ""))]
+  [(set (zero_extract (match_operand 0 "ext_register_operand" "")
+                     (match_operand 1 "immediate_operand" "")
+                     (match_operand 2 "immediate_operand" ""))
+        (match_operand 3 "register_operand" ""))]
   ""
 {
   /* Handle extractions from %ah et al.  */
@@ -12628,6 +12628,13 @@
      matches the predicate, so check it again here.  */
   if (! register_operand (operands[0], VOIDmode))
     FAIL;
+
+  if (TARGET_64BIT)
+    emit_insn (gen_movdi_insv_1_rex64 (operands[0], operands[3]));
+  else
+    emit_insn (gen_movsi_insv_1 (operands[0], operands[3]));
+
+  DONE;
 })
 
 ;; %%% bts, btr, btc, bt.