RISC-V: Added Zfhmin and Zhinxmin.

This commit adds Zfhmin and Zhinxmin extensions (subsets of Zfh and
Zhinx extensions, respectively).  In the process supporting Zfhmin and
Zhinxmin extension, this commit also changes how instructions are
categorized considering Zfhmin, Zhinx and Zhinxmin extensions.

Detailed changes,

* From INSN_CLASS_ZFH to INSN_CLASS_ZFHMIN:

flh, fsh, fmv.x.h and fmv.h.x.

* From INSN_CLASS_ZFH to INSN_CLASS_ZFH_OR_ZHINX:

fmv.h.

* From INSN_CLASS_ZFH_OR_ZHINX to INSN_CLASS_ZFH_OR_ZHINX:

fneg.h, fabs.h, fsgnj.h, fsgnjn.h, fsgnjx.h,
fadd.h, fsub.h, fmul.h, fdiv.h, fsqrt.h, fmin.h, fmax.h,
fmadd.h, fnmadd.h, fmsub.h, fnmsub.h,
fcvt.w.h, fcvt.wu.h, fcvt.h.w, fcvt.h.wu,
fcvt.l.h, fcvt.lu.h, fcvt.h.l, fcvt.h.lu,
feq.h, flt.h, fle.h, fgt.h, fge.h,
fclass.h.

* From INSN_CLASS_ZFH_OR_ZHINX to INSN_CLASS_ZFHMIN_OR_ZHINXMIN:

fcvt.s.h and fcvt.h.s.

* From INSN_CLASS_D_AND_ZFH_INX to INSN_CLASS_ZFHMIN_AND_D:

fcvt.d.h and fcvt.h.d.

* From INSN_CLASS_Q_AND_ZFH_INX to INSN_CLASS_ZFHMIN_AND_Q:

fcvt.q.h and fcvt.h.q.

bfd/ChangeLog:

	* elfxx-riscv.c (riscv_implicit_subsets): Change implicit
	subsets.  Zfh->Zicsr is not needed and Zfh->F is replaced with
	Zfh->Zfhmin and Zfhmin->F.  Zhinx->Zicsr is not needed and
	Zhinx->Zfinx is replaced with Zhinx->Zhinxmin and
	Zhinxmin->Zfinx.
	(riscv_supported_std_z_ext): Added zfhmin and zhinxmin.
	(riscv_multi_subset_supports):  Rewrite handling for new
	instruction classes.
	(riscv_multi_subset_supports_ext): Updated.
	(riscv_parse_check_conflicts): Change error message to include
	zfh and zfhmin extensions.

gas/ChangeLog:

	* testsuite/gas/riscv/zfhmin-d-insn-class-fail.s: New complex
	error handling test.
	* testsuite/gas/riscv/zfhmin-d-insn-class-fail-1.d: Likewise.
	* testsuite/gas/riscv/zfhmin-d-insn-class-fail-1.l: Likewise.
	* testsuite/gas/riscv/zfhmin-d-insn-class-fail-2.d: Likewise.
	* testsuite/gas/riscv/zfhmin-d-insn-class-fail-2.l: Likewise.
	* testsuite/gas/riscv/zfhmin-d-insn-class-fail-3.d: Likewise.
	* testsuite/gas/riscv/zfhmin-d-insn-class-fail-3.l: Likewise.
	* testsuite/gas/riscv/zfhmin-d-insn-class-fail-4.d: Likewise.
	* testsuite/gas/riscv/zfhmin-d-insn-class-fail-4.l: Likewise.
	* testsuite/gas/riscv/zfhmin-d-insn-class-fail-5.d: Likewise.
	* testsuite/gas/riscv/zfhmin-d-insn-class-fail-5.l: Likewise.
	* testsuite/gas/riscv/zhinx.d: Renamed from fp-zhinx-insns.d
	and refactored.
	* testsuite/gas/riscv/zhinx.s: Likewise.

include/ChangeLog:

	* opcode/riscv.h (enum riscv_insn_class): Removed INSN_CLASS_ZFH,
	INSN_CLASS_D_AND_ZFH_INX and INSN_CLASS_Q_AND_ZFH_INX.  Added
	INSN_CLASS_ZFHMIN, INSN_CLASS_ZFHMIN_OR_ZHINXMIN,
	INSN_CLASS_ZFHMIN_AND_D and INSN_CLASS_ZFHMIN_AND_Q.

opcodes/ChangeLog:

	* riscv-opc.c (riscv_opcodes): Change instruction classes for
	Zfh and Zfhmin instructions.  Fix `fcvt.h.lu' instruction
	(two operand variant) mask.

diff --git a/bfd/elfxx-riscv.c b/bfd/elfxx-riscv.c
index 7d0825404dff9ff8b5ca48340b5af6bd4c30cccf..0b2021f5cc7903c93c27aced475fdc9ff45fb99d 100644 (file)
--- a/bfd/elfxx-riscv.c
+++ b/bfd/elfxx-riscv.c
@@ -1099,14 +1099,14 @@ static struct riscv_implicit_subset riscv_implicit_subsets[] =
   {"zvl128b", "zvl64b",                check_implicit_always},
   {"zvl64b", "zvl32b",         check_implicit_always},
   {"d", "f",           check_implicit_always},
+  {"zfh", "zfhmin",    check_implicit_always},
+  {"zfhmin", "f",      check_implicit_always},
   {"f", "zicsr",       check_implicit_always},
-  {"zfh", "f",         check_implicit_always},
-  {"zfh", "zicsr",     check_implicit_always},
   {"zqinx", "zdinx",   check_implicit_always},
   {"zdinx", "zfinx",   check_implicit_always},
+  {"zhinx", "zhinxmin",        check_implicit_always},
+  {"zhinxmin", "zfinx",        check_implicit_always},
   {"zfinx", "zicsr",   check_implicit_always},
-  {"zhinx", "zfinx",   check_implicit_always},
-  {"zhinx", "zicsr",   check_implicit_always},
   {"zk", "zkn",                check_implicit_always},
   {"zk", "zkr",                check_implicit_always},
   {"zk", "zkt",                check_implicit_always},
@@ -1187,10 +1187,12 @@ static struct riscv_supported_ext riscv_supported_std_z_ext[] =
   {"zifencei",         ISA_SPEC_CLASS_20190608,        2, 0,  0 },
   {"zihintpause",      ISA_SPEC_CLASS_DRAFT,           2, 0,  0 },
   {"zfh",              ISA_SPEC_CLASS_DRAFT,           1, 0,  0 },
+  {"zfhmin",           ISA_SPEC_CLASS_DRAFT,           1, 0,  0 },
   {"zfinx",            ISA_SPEC_CLASS_DRAFT,           1, 0,  0 },
   {"zdinx",            ISA_SPEC_CLASS_DRAFT,           1, 0,  0 },
   {"zqinx",            ISA_SPEC_CLASS_DRAFT,           1, 0,  0 },
   {"zhinx",            ISA_SPEC_CLASS_DRAFT,           1, 0,  0 },
+  {"zhinxmin",         ISA_SPEC_CLASS_DRAFT,           1, 0,  0 },
   {"zbb",              ISA_SPEC_CLASS_DRAFT,           1, 0,  0 },
   {"zba",              ISA_SPEC_CLASS_DRAFT,           1, 0,  0 },
   {"zbc",              ISA_SPEC_CLASS_DRAFT,           1, 0,  0 },
@@ -1878,7 +1880,7 @@ riscv_parse_check_conflicts (riscv_parse_subset_t *rps)
       && riscv_lookup_subset (rps->subset_list, "f", &subset))
     {
       rps->error_handler
-       (_("`zfinx' is conflict with the `f/d/q' extension"));
+       (_("`zfinx' is conflict with the `f/d/q/zfh/zfhmin' extension"));
       no_conflict = false;
     }
 
@@ -2336,21 +2338,24 @@ riscv_multi_subset_supports (riscv_parse_subset_t *rps,
     case INSN_CLASS_Q_OR_ZQINX:
       return (riscv_subset_supports (rps, "q")
              || riscv_subset_supports (rps, "zqinx"));
-    case INSN_CLASS_ZFH:
-      return riscv_subset_supports (rps, "zfh");
     case INSN_CLASS_ZFH_OR_ZHINX:
-      return riscv_subset_supports (rps, "zfh")
-            || riscv_subset_supports (rps, "zhinx");
-    case INSN_CLASS_D_AND_ZFH_INX:
-      return (riscv_subset_supports (rps, "d")
-             && riscv_subset_supports (rps, "zfh"))
-            || (riscv_subset_supports (rps, "zdinx")
-                && riscv_subset_supports (rps, "zhinx"));
-    case INSN_CLASS_Q_AND_ZFH_INX:
-      return (riscv_subset_supports (rps, "q")
-             && riscv_subset_supports (rps, "zfh"))
-            || (riscv_subset_supports (rps, "zqinx")
-                && riscv_subset_supports (rps, "zhinx"));
+      return (riscv_subset_supports (rps, "zfh")
+             || riscv_subset_supports (rps, "zhinx"));
+    case INSN_CLASS_ZFHMIN:
+      return riscv_subset_supports (rps, "zfhmin");
+    case INSN_CLASS_ZFHMIN_OR_ZHINXMIN:
+      return (riscv_subset_supports (rps, "zfhmin")
+             || riscv_subset_supports (rps, "zhinxmin"));
+    case INSN_CLASS_ZFHMIN_AND_D:
+      return ((riscv_subset_supports (rps, "zfhmin")
+              && riscv_subset_supports (rps, "d"))
+             || (riscv_subset_supports (rps, "zhinxmin")
+                 && riscv_subset_supports (rps, "zdinx")));
+    case INSN_CLASS_ZFHMIN_AND_Q:
+      return ((riscv_subset_supports (rps, "zfhmin")
+              && riscv_subset_supports (rps, "q"))
+             || (riscv_subset_supports (rps, "zhinxmin")
+                 && riscv_subset_supports (rps, "zqinx")));
     case INSN_CLASS_ZBA:
       return riscv_subset_supports (rps, "zba");
     case INSN_CLASS_ZBB:
@@ -2456,6 +2461,34 @@ riscv_multi_subset_supports_ext (riscv_parse_subset_t *rps,
       return _("d' or `zdinx");
     case INSN_CLASS_Q_OR_ZQINX:
       return _("q' or `zqinx");
+    case INSN_CLASS_ZFH_OR_ZHINX:
+      return _("zfh' or `zhinx");
+    case INSN_CLASS_ZFHMIN:
+      return "zfhmin";
+    case INSN_CLASS_ZFHMIN_OR_ZHINXMIN:
+      return _("zfhmin' or `zhinxmin");
+    case INSN_CLASS_ZFHMIN_AND_D:
+      if (riscv_subset_supports (rps, "zfhmin"))
+       return "d";
+      else if (riscv_subset_supports (rps, "d"))
+       return "zfhmin";
+      else if (riscv_subset_supports (rps, "zhinxmin"))
+       return "zdinx";
+      else if (riscv_subset_supports (rps, "zdinx"))
+       return "zhinxmin";
+      else
+       return _("zfhmin' and `d', or `zhinxmin' and `zdinx");
+    case INSN_CLASS_ZFHMIN_AND_Q:
+      if (riscv_subset_supports (rps, "zfhmin"))
+       return "q";
+      else if (riscv_subset_supports (rps, "q"))
+       return "zfhmin";
+      else if (riscv_subset_supports (rps, "zhinxmin"))
+       return "zqinx";
+      else if (riscv_subset_supports (rps, "zqinx"))
+       return "zhinxmin";
+      else
+       return _("zfhmin' and `q', or `zhinxmin' and `zqinx");
     case INSN_CLASS_ZBA:
       return "zba";
     case INSN_CLASS_ZBB:
@@ -2492,32 +2525,6 @@ riscv_multi_subset_supports_ext (riscv_parse_subset_t *rps,
       return _("v' or `zve64d' or `zve64f' or `zve32f");
     case INSN_CLASS_SVINVAL:
       return "svinval";
-    case INSN_CLASS_ZFH:
-      return "zfh";
-    case INSN_CLASS_ZFH_OR_ZHINX:
-      return _("zfh' or 'zhinx");
-    case INSN_CLASS_D_AND_ZFH_INX:
-      if (riscv_subset_supports (rps, "zfh"))
-       return "d";
-      else if (riscv_subset_supports (rps, "d"))
-       return "zfh";
-      else if (riscv_subset_supports (rps, "zhinx"))
-       return "zdinx";
-      else if (riscv_subset_supports (rps, "zdinx"))
-       return "zhinx";
-      else
-       return _("zfh' and `d', or `zhinx' and `zdinx");
-    case INSN_CLASS_Q_AND_ZFH_INX:
-      if (riscv_subset_supports (rps, "zfh"))
-       return "q";
-      else if (riscv_subset_supports (rps, "q"))
-       return "zfh";
-      else if (riscv_subset_supports (rps, "zhinx"))
-       return "zqinx";
-      else if (riscv_subset_supports (rps, "zqinx"))
-       return "zhinx";
-      else
-       return _("zfh' and `q', or `zhinx' and `zqinx");
     case INSN_CLASS_H:
       return _("h");
     default:

diff --git a/gas/testsuite/gas/riscv/fp-zhinx-insns.d b/gas/testsuite/gas/riscv/fp-zhinx-insns.d
deleted file mode 100644 (file)
index 2592d8c..0000000
--- a/gas/testsuite/gas/riscv/fp-zhinx-insns.d
+++ /dev/null
@@ -1,66 +0,0 @@
-#as: -march=rv64ima_zqinx_zhinx
-#source: fp-zhinx-insns.s
-#objdump: -dr
-
-.*:[   ]+file format .*
-
-
-Disassembly of section .text:
-
-0+000 <.text>:
-[      ]+[0-9a-f]+:[   ]+24b59553[     ]+fneg.h[       ]+a0,a1
-[      ]+[0-9a-f]+:[   ]+24b5a553[     ]+fabs.h[       ]+a0,a1
-[      ]+[0-9a-f]+:[   ]+24c58553[     ]+fsgnj.h[      ]+a0,a1,a2
-[      ]+[0-9a-f]+:[   ]+24c59553[     ]+fsgnjn.h[     ]+a0,a1,a2
-[      ]+[0-9a-f]+:[   ]+24c5a553[     ]+fsgnjx.h[     ]+a0,a1,a2
-[      ]+[0-9a-f]+:[   ]+04c5f553[     ]+fadd.h[       ]+a0,a1,a2
-[      ]+[0-9a-f]+:[   ]+04c58553[     ]+fadd.h[       ]+a0,a1,a2,rne
-[      ]+[0-9a-f]+:[   ]+0cc5f553[     ]+fsub.h[       ]+a0,a1,a2
-[      ]+[0-9a-f]+:[   ]+0cc58553[     ]+fsub.h[       ]+a0,a1,a2,rne
-[      ]+[0-9a-f]+:[   ]+14c5f553[     ]+fmul.h[       ]+a0,a1,a2
-[      ]+[0-9a-f]+:[   ]+14c58553[     ]+fmul.h[       ]+a0,a1,a2,rne
-[      ]+[0-9a-f]+:[   ]+1cc5f553[     ]+fdiv.h[       ]+a0,a1,a2
-[      ]+[0-9a-f]+:[   ]+1cc58553[     ]+fdiv.h[       ]+a0,a1,a2,rne
-[      ]+[0-9a-f]+:[   ]+5c05f553[     ]+fsqrt.h[      ]+a0,a1
-[      ]+[0-9a-f]+:[   ]+5c058553[     ]+fsqrt.h[      ]+a0,a1,rne
-[      ]+[0-9a-f]+:[   ]+2cc58553[     ]+fmin.h[       ]+a0,a1,a2
-[      ]+[0-9a-f]+:[   ]+2cc59553[     ]+fmax.h[       ]+a0,a1,a2
-[      ]+[0-9a-f]+:[   ]+6cc5f543[     ]+fmadd.h[      ]+a0,a1,a2,a3
-[      ]+[0-9a-f]+:[   ]+6cc58543[     ]+fmadd.h[      ]+a0,a1,a2,a3,rne
-[      ]+[0-9a-f]+:[   ]+6cc5f54f[     ]+fnmadd.h[     ]+a0,a1,a2,a3
-[      ]+[0-9a-f]+:[   ]+6cc5854f[     ]+fnmadd.h[     ]+a0,a1,a2,a3,rne
-[      ]+[0-9a-f]+:[   ]+6cc5f547[     ]+fmsub.h[      ]+a0,a1,a2,a3
-[      ]+[0-9a-f]+:[   ]+6cc58547[     ]+fmsub.h[      ]+a0,a1,a2,a3,rne
-[      ]+[0-9a-f]+:[   ]+6cc5f54b[     ]+fnmsub.h[     ]+a0,a1,a2,a3
-[      ]+[0-9a-f]+:[   ]+6cc5854b[     ]+fnmsub.h[     ]+a0,a1,a2,a3,rne
-[      ]+[0-9a-f]+:[   ]+c405f553[     ]+fcvt.w.h[     ]+a0,a1
-[      ]+[0-9a-f]+:[   ]+c4058553[     ]+fcvt.w.h[     ]+a0,a1,rne
-[      ]+[0-9a-f]+:[   ]+c415f553[     ]+fcvt.wu.h[    ]+a0,a1
-[      ]+[0-9a-f]+:[   ]+c4158553[     ]+fcvt.wu.h[    ]+a0,a1,rne
-[      ]+[0-9a-f]+:[   ]+d405f553[     ]+fcvt.h.w[     ]+a0,a1
-[      ]+[0-9a-f]+:[   ]+d4058553[     ]+fcvt.h.w[     ]+a0,a1,rne
-[      ]+[0-9a-f]+:[   ]+d415f553[     ]+fcvt.h.wu[    ]+a0,a1
-[      ]+[0-9a-f]+:[   ]+d4158553[     ]+fcvt.h.wu[    ]+a0,a1,rne
-[      ]+[0-9a-f]+:[   ]+c425f553[     ]+fcvt.l.h[     ]+a0,a1
-[      ]+[0-9a-f]+:[   ]+c4258553[     ]+fcvt.l.h[     ]+a0,a1,rne
-[      ]+[0-9a-f]+:[   ]+c435f553[     ]+fcvt.lu.h[    ]+a0,a1
-[      ]+[0-9a-f]+:[   ]+c4358553[     ]+fcvt.lu.h[    ]+a0,a1,rne
-[      ]+[0-9a-f]+:[   ]+d425f553[     ]+fcvt.h.l[     ]+a0,a1
-[      ]+[0-9a-f]+:[   ]+d4258553[     ]+fcvt.h.l[     ]+a0,a1,rne
-[      ]+[0-9a-f]+:[   ]+d435f553[     ]+fcvt.h.lu[    ]+a0,a1
-[      ]+[0-9a-f]+:[   ]+d4358553[     ]+fcvt.h.lu[    ]+a0,a1,rne
-[      ]+[0-9a-f]+:[   ]+40258553[     ]+fcvt.s.h[     ]+a0,a1
-[      ]+[0-9a-f]+:[   ]+42258553[     ]+fcvt.d.h[     ]+a0,a1
-[      ]+[0-9a-f]+:[   ]+46258553[     ]+fcvt.q.h[     ]+a0,a1
-[      ]+[0-9a-f]+:[   ]+4405f553[     ]+fcvt.h.s[     ]+a0,a1
-[      ]+[0-9a-f]+:[   ]+44058553[     ]+fcvt.h.s[     ]+a0,a1,rne
-[      ]+[0-9a-f]+:[   ]+4415f553[     ]+fcvt.h.d[     ]+a0,a1
-[      ]+[0-9a-f]+:[   ]+44158553[     ]+fcvt.h.d[     ]+a0,a1,rne
-[      ]+[0-9a-f]+:[   ]+4435f553[     ]+fcvt.h.q[     ]+a0,a1
-[      ]+[0-9a-f]+:[   ]+44358553[     ]+fcvt.h.q[     ]+a0,a1,rne
-[      ]+[0-9a-f]+:[   ]+e4059553[     ]+fclass.h[     ]+a0,a1
-[      ]+[0-9a-f]+:[   ]+a4c5a553[     ]+feq.h[        ]+a0,a1,a2
-[      ]+[0-9a-f]+:[   ]+a4c59553[     ]+flt.h[        ]+a0,a1,a2
-[      ]+[0-9a-f]+:[   ]+a4c58553[     ]+fle.h[        ]+a0,a1,a2
-[      ]+[0-9a-f]+:[   ]+a4c59553[     ]+flt.h[        ]+a0,a1,a2
-[      ]+[0-9a-f]+:[   ]+a4c58553[     ]+fle.h[        ]+a0,a1,a2

diff --git a/gas/testsuite/gas/riscv/fp-zhinx-insns.s b/gas/testsuite/gas/riscv/fp-zhinx-insns.s
deleted file mode 100644 (file)
index 75e2d5a..0000000
--- a/gas/testsuite/gas/riscv/fp-zhinx-insns.s
+++ /dev/null
@@ -1,59 +0,0 @@
-       fneg.h          a0, a1
-       fabs.h          a0, a1
-       fsgnj.h         a0, a1, a2
-       fsgnjn.h        a0, a1, a2
-       fsgnjx.h        a0, a1, a2
-       fadd.h          a0, a1, a2
-       fadd.h          a0, a1, a2, rne
-       fsub.h          a0, a1, a2
-       fsub.h          a0, a1, a2, rne
-       fmul.h          a0, a1, a2
-       fmul.h          a0, a1, a2, rne
-       fdiv.h          a0, a1, a2
-       fdiv.h          a0, a1, a2, rne
-       fsqrt.h         a0, a1
-       fsqrt.h         a0, a1, rne
-       fmin.h          a0, a1, a2
-       fmax.h          a0, a1, a2
-       fmadd.h         a0, a1, a2, a3
-       fmadd.h         a0, a1, a2, a3, rne
-       fnmadd.h        a0, a1, a2, a3
-       fnmadd.h        a0, a1, a2, a3, rne
-       fmsub.h         a0, a1, a2, a3
-       fmsub.h         a0, a1, a2, a3, rne
-       fnmsub.h        a0, a1, a2, a3
-       fnmsub.h        a0, a1, a2, a3, rne
-
-       fcvt.w.h        a0, a1
-       fcvt.w.h        a0, a1, rne
-       fcvt.wu.h       a0, a1
-       fcvt.wu.h       a0, a1, rne
-       fcvt.h.w        a0, a1
-       fcvt.h.w        a0, a1, rne
-       fcvt.h.wu       a0, a1
-       fcvt.h.wu       a0, a1, rne
-       fcvt.l.h        a0, a1
-       fcvt.l.h        a0, a1, rne
-       fcvt.lu.h       a0, a1
-       fcvt.lu.h       a0, a1, rne
-       fcvt.h.l        a0, a1
-       fcvt.h.l        a0, a1, rne
-       fcvt.h.lu       a0, a1
-       fcvt.h.lu       a0, a1, rne
-
-       fcvt.s.h        a0, a1
-       fcvt.d.h        a0, a1
-       fcvt.q.h        a0, a1
-       fcvt.h.s        a0, a1
-       fcvt.h.s        a0, a1, rne
-       fcvt.h.d        a0, a1
-       fcvt.h.d        a0, a1, rne
-       fcvt.h.q        a0, a1
-       fcvt.h.q        a0, a1, rne
-       fclass.h        a0, a1
-
-       feq.h           a0, a1, a2
-       flt.h           a0, a1, a2
-       fle.h           a0, a1, a2
-       fgt.h           a0, a2, a1
-       fge.h           a0, a2, a1

diff --git a/gas/testsuite/gas/riscv/zfhmin-d-insn-class-fail-1.d b/gas/testsuite/gas/riscv/zfhmin-d-insn-class-fail-1.d
new file mode 100644 (file)
index 0000000..02a1194
--- /dev/null
+++ b/gas/testsuite/gas/riscv/zfhmin-d-insn-class-fail-1.d
@@ -0,0 +1,3 @@
+#as: -march=rv64i
+#source: zfhmin-d-insn-class-fail.s
+#error_output: zfhmin-d-insn-class-fail-1.l

diff --git a/gas/testsuite/gas/riscv/zfhmin-d-insn-class-fail-1.l b/gas/testsuite/gas/riscv/zfhmin-d-insn-class-fail-1.l
new file mode 100644 (file)
index 0000000..12f41a3
--- /dev/null
+++ b/gas/testsuite/gas/riscv/zfhmin-d-insn-class-fail-1.l
@@ -0,0 +1,2 @@
+.*: Assembler messages:
+.*: Error: unrecognized opcode `fcvt.d.h fa0,fa1', extension `zfhmin' and `d', or `zhinxmin' and `zdinx' required

diff --git a/gas/testsuite/gas/riscv/zfhmin-d-insn-class-fail-2.d b/gas/testsuite/gas/riscv/zfhmin-d-insn-class-fail-2.d
new file mode 100644 (file)
index 0000000..27b5a12
--- /dev/null
+++ b/gas/testsuite/gas/riscv/zfhmin-d-insn-class-fail-2.d
@@ -0,0 +1,3 @@
+#as: -march=rv64i_zhinxmin
+#source: zfhmin-d-insn-class-fail.s
+#error_output: zfhmin-d-insn-class-fail-2.l

diff --git a/gas/testsuite/gas/riscv/zfhmin-d-insn-class-fail-2.l b/gas/testsuite/gas/riscv/zfhmin-d-insn-class-fail-2.l
new file mode 100644 (file)
index 0000000..255f96c
--- /dev/null
+++ b/gas/testsuite/gas/riscv/zfhmin-d-insn-class-fail-2.l
@@ -0,0 +1,2 @@
+.*: Assembler messages:
+.*: Error: unrecognized opcode `fcvt.d.h fa0,fa1', extension `zdinx' required

diff --git a/gas/testsuite/gas/riscv/zfhmin-d-insn-class-fail-3.d b/gas/testsuite/gas/riscv/zfhmin-d-insn-class-fail-3.d
new file mode 100644 (file)
index 0000000..4f195bf
--- /dev/null
+++ b/gas/testsuite/gas/riscv/zfhmin-d-insn-class-fail-3.d
@@ -0,0 +1,3 @@
+#as: -march=rv64i_zdinx
+#source: zfhmin-d-insn-class-fail.s
+#error_output: zfhmin-d-insn-class-fail-3.l

diff --git a/gas/testsuite/gas/riscv/zfhmin-d-insn-class-fail-3.l b/gas/testsuite/gas/riscv/zfhmin-d-insn-class-fail-3.l
new file mode 100644 (file)
index 0000000..7ff7b27
--- /dev/null
+++ b/gas/testsuite/gas/riscv/zfhmin-d-insn-class-fail-3.l
@@ -0,0 +1,2 @@
+.*: Assembler messages:
+.*: Error: unrecognized opcode `fcvt.d.h fa0,fa1', extension `zhinxmin' required

diff --git a/gas/testsuite/gas/riscv/zfhmin-d-insn-class-fail-4.d b/gas/testsuite/gas/riscv/zfhmin-d-insn-class-fail-4.d
new file mode 100644 (file)
index 0000000..940d48c
--- /dev/null
+++ b/gas/testsuite/gas/riscv/zfhmin-d-insn-class-fail-4.d
@@ -0,0 +1,3 @@
+#as: -march=rv64i_zfhmin
+#source: zfhmin-d-insn-class-fail.s
+#error_output: zfhmin-d-insn-class-fail-4.l

diff --git a/gas/testsuite/gas/riscv/zfhmin-d-insn-class-fail-4.l b/gas/testsuite/gas/riscv/zfhmin-d-insn-class-fail-4.l
new file mode 100644 (file)
index 0000000..2d58e4c
--- /dev/null
+++ b/gas/testsuite/gas/riscv/zfhmin-d-insn-class-fail-4.l
@@ -0,0 +1,2 @@
+.*: Assembler messages:
+.*: Error: unrecognized opcode `fcvt.d.h fa0,fa1', extension `d' required

diff --git a/gas/testsuite/gas/riscv/zfhmin-d-insn-class-fail-5.d b/gas/testsuite/gas/riscv/zfhmin-d-insn-class-fail-5.d
new file mode 100644 (file)
index 0000000..af26d5e
--- /dev/null
+++ b/gas/testsuite/gas/riscv/zfhmin-d-insn-class-fail-5.d
@@ -0,0 +1,3 @@
+#as: -march=rv64id
+#source: zfhmin-d-insn-class-fail.s
+#error_output: zfhmin-d-insn-class-fail-5.l

diff --git a/gas/testsuite/gas/riscv/zfhmin-d-insn-class-fail-5.l b/gas/testsuite/gas/riscv/zfhmin-d-insn-class-fail-5.l
new file mode 100644 (file)
index 0000000..2fa6e8c
--- /dev/null
+++ b/gas/testsuite/gas/riscv/zfhmin-d-insn-class-fail-5.l
@@ -0,0 +1,2 @@
+.*: Assembler messages:
+.*: Error: unrecognized opcode `fcvt.d.h fa0,fa1', extension `zfhmin' required

diff --git a/gas/testsuite/gas/riscv/zfhmin-d-insn-class-fail.s b/gas/testsuite/gas/riscv/zfhmin-d-insn-class-fail.s
new file mode 100644 (file)
index 0000000..691d0a9
--- /dev/null
+++ b/gas/testsuite/gas/riscv/zfhmin-d-insn-class-fail.s
@@ -0,0 +1,4 @@
+# This test checks error message corresponding required extension(s).
+# Operands are invalid on Zhinxmin+Zdinx but they are not parsed since
+# extension test fails.
+fcvt.d.h       fa0, fa1

diff --git a/gas/testsuite/gas/riscv/zhinx.d b/gas/testsuite/gas/riscv/zhinx.d
new file mode 100644 (file)
index 0000000..eb98914
--- /dev/null
+++ b/gas/testsuite/gas/riscv/zhinx.d
@@ -0,0 +1,67 @@
+#as: -march=rv64ima_zqinx_zhinx
+#source: zhinx.s
+#objdump: -dr
+
+.*:[   ]+file format .*
+
+
+Disassembly of section .text:
+
+0+000 <target>:
+[      ]+[0-9a-f]+:[   ]+04c5f553[     ]+fadd.h[       ]+a0,a1,a2
+[      ]+[0-9a-f]+:[   ]+04c58553[     ]+fadd.h[       ]+a0,a1,a2,rne
+[      ]+[0-9a-f]+:[   ]+0cc5f553[     ]+fsub.h[       ]+a0,a1,a2
+[      ]+[0-9a-f]+:[   ]+0cc58553[     ]+fsub.h[       ]+a0,a1,a2,rne
+[      ]+[0-9a-f]+:[   ]+14c5f553[     ]+fmul.h[       ]+a0,a1,a2
+[      ]+[0-9a-f]+:[   ]+14c58553[     ]+fmul.h[       ]+a0,a1,a2,rne
+[      ]+[0-9a-f]+:[   ]+1cc5f553[     ]+fdiv.h[       ]+a0,a1,a2
+[      ]+[0-9a-f]+:[   ]+1cc58553[     ]+fdiv.h[       ]+a0,a1,a2,rne
+[      ]+[0-9a-f]+:[   ]+5c05f553[     ]+fsqrt.h[      ]+a0,a1
+[      ]+[0-9a-f]+:[   ]+5c058553[     ]+fsqrt.h[      ]+a0,a1,rne
+[      ]+[0-9a-f]+:[   ]+2cc58553[     ]+fmin.h[       ]+a0,a1,a2
+[      ]+[0-9a-f]+:[   ]+2cc59553[     ]+fmax.h[       ]+a0,a1,a2
+[      ]+[0-9a-f]+:[   ]+6cc5f543[     ]+fmadd.h[      ]+a0,a1,a2,a3
+[      ]+[0-9a-f]+:[   ]+6cc58543[     ]+fmadd.h[      ]+a0,a1,a2,a3,rne
+[      ]+[0-9a-f]+:[   ]+6cc5f54f[     ]+fnmadd.h[     ]+a0,a1,a2,a3
+[      ]+[0-9a-f]+:[   ]+6cc5854f[     ]+fnmadd.h[     ]+a0,a1,a2,a3,rne
+[      ]+[0-9a-f]+:[   ]+6cc5f547[     ]+fmsub.h[      ]+a0,a1,a2,a3
+[      ]+[0-9a-f]+:[   ]+6cc58547[     ]+fmsub.h[      ]+a0,a1,a2,a3,rne
+[      ]+[0-9a-f]+:[   ]+6cc5f54b[     ]+fnmsub.h[     ]+a0,a1,a2,a3
+[      ]+[0-9a-f]+:[   ]+6cc5854b[     ]+fnmsub.h[     ]+a0,a1,a2,a3,rne
+[      ]+[0-9a-f]+:[   ]+c405f553[     ]+fcvt.w.h[     ]+a0,a1
+[      ]+[0-9a-f]+:[   ]+c4058553[     ]+fcvt.w.h[     ]+a0,a1,rne
+[      ]+[0-9a-f]+:[   ]+c415f553[     ]+fcvt.wu.h[    ]+a0,a1
+[      ]+[0-9a-f]+:[   ]+c4158553[     ]+fcvt.wu.h[    ]+a0,a1,rne
+[      ]+[0-9a-f]+:[   ]+d405f553[     ]+fcvt.h.w[     ]+a0,a1
+[      ]+[0-9a-f]+:[   ]+d4058553[     ]+fcvt.h.w[     ]+a0,a1,rne
+[      ]+[0-9a-f]+:[   ]+d415f553[     ]+fcvt.h.wu[    ]+a0,a1
+[      ]+[0-9a-f]+:[   ]+d4158553[     ]+fcvt.h.wu[    ]+a0,a1,rne
+[      ]+[0-9a-f]+:[   ]+c425f553[     ]+fcvt.l.h[     ]+a0,a1
+[      ]+[0-9a-f]+:[   ]+c4258553[     ]+fcvt.l.h[     ]+a0,a1,rne
+[      ]+[0-9a-f]+:[   ]+c435f553[     ]+fcvt.lu.h[    ]+a0,a1
+[      ]+[0-9a-f]+:[   ]+c4358553[     ]+fcvt.lu.h[    ]+a0,a1,rne
+[      ]+[0-9a-f]+:[   ]+d425f553[     ]+fcvt.h.l[     ]+a0,a1
+[      ]+[0-9a-f]+:[   ]+d4258553[     ]+fcvt.h.l[     ]+a0,a1,rne
+[      ]+[0-9a-f]+:[   ]+d435f553[     ]+fcvt.h.lu[    ]+a0,a1
+[      ]+[0-9a-f]+:[   ]+d4358553[     ]+fcvt.h.lu[    ]+a0,a1,rne
+[      ]+[0-9a-f]+:[   ]+40260553[     ]+fcvt.s.h[     ]+a0,a2
+[      ]+[0-9a-f]+:[   ]+42260553[     ]+fcvt.d.h[     ]+a0,a2
+[      ]+[0-9a-f]+:[   ]+46260553[     ]+fcvt.q.h[     ]+a0,a2
+[      ]+[0-9a-f]+:[   ]+44067553[     ]+fcvt.h.s[     ]+a0,a2
+[      ]+[0-9a-f]+:[   ]+44060553[     ]+fcvt.h.s[     ]+a0,a2,rne
+[      ]+[0-9a-f]+:[   ]+44167553[     ]+fcvt.h.d[     ]+a0,a2
+[      ]+[0-9a-f]+:[   ]+44160553[     ]+fcvt.h.d[     ]+a0,a2,rne
+[      ]+[0-9a-f]+:[   ]+44367553[     ]+fcvt.h.q[     ]+a0,a2
+[      ]+[0-9a-f]+:[   ]+44360553[     ]+fcvt.h.q[     ]+a0,a2,rne
+[      ]+[0-9a-f]+:[   ]+24c58553[     ]+fsgnj.h[      ]+a0,a1,a2
+[      ]+[0-9a-f]+:[   ]+24c59553[     ]+fsgnjn.h[     ]+a0,a1,a2
+[      ]+[0-9a-f]+:[   ]+24c5a553[     ]+fsgnjx.h[     ]+a0,a1,a2
+[      ]+[0-9a-f]+:[   ]+a4c5a553[     ]+feq.h[        ]+a0,a1,a2
+[      ]+[0-9a-f]+:[   ]+a4c59553[     ]+flt.h[        ]+a0,a1,a2
+[      ]+[0-9a-f]+:[   ]+a4c58553[     ]+fle.h[        ]+a0,a1,a2
+[      ]+[0-9a-f]+:[   ]+a4c59553[     ]+flt.h[        ]+a0,a1,a2
+[      ]+[0-9a-f]+:[   ]+a4c58553[     ]+fle.h[        ]+a0,a1,a2
+[      ]+[0-9a-f]+:[   ]+24b58553[     ]+fmv.h[        ]+a0,a1
+[      ]+[0-9a-f]+:[   ]+24b59553[     ]+fneg.h[       ]+a0,a1
+[      ]+[0-9a-f]+:[   ]+24b5a553[     ]+fabs.h[       ]+a0,a1
+[      ]+[0-9a-f]+:[   ]+e4059553[     ]+fclass.h[     ]+a0,a1

diff --git a/gas/testsuite/gas/riscv/zhinx.s b/gas/testsuite/gas/riscv/zhinx.s
new file mode 100644 (file)
index 0000000..05eff34
--- /dev/null
+++ b/gas/testsuite/gas/riscv/zhinx.s
@@ -0,0 +1,61 @@
+target:
+       fadd.h          a0, a1, a2
+       fadd.h          a0, a1, a2, rne
+       fsub.h          a0, a1, a2
+       fsub.h          a0, a1, a2, rne
+       fmul.h          a0, a1, a2
+       fmul.h          a0, a1, a2, rne
+       fdiv.h          a0, a1, a2
+       fdiv.h          a0, a1, a2, rne
+       fsqrt.h         a0, a1
+       fsqrt.h         a0, a1, rne
+       fmin.h          a0, a1, a2
+       fmax.h          a0, a1, a2
+       fmadd.h         a0, a1, a2, a3
+       fmadd.h         a0, a1, a2, a3, rne
+       fnmadd.h        a0, a1, a2, a3
+       fnmadd.h        a0, a1, a2, a3, rne
+       fmsub.h         a0, a1, a2, a3
+       fmsub.h         a0, a1, a2, a3, rne
+       fnmsub.h        a0, a1, a2, a3
+       fnmsub.h        a0, a1, a2, a3, rne
+
+       fcvt.w.h        a0, a1
+       fcvt.w.h        a0, a1, rne
+       fcvt.wu.h       a0, a1
+       fcvt.wu.h       a0, a1, rne
+       fcvt.h.w        a0, a1
+       fcvt.h.w        a0, a1, rne
+       fcvt.h.wu       a0, a1
+       fcvt.h.wu       a0, a1, rne
+       fcvt.l.h        a0, a1
+       fcvt.l.h        a0, a1, rne
+       fcvt.lu.h       a0, a1
+       fcvt.lu.h       a0, a1, rne
+       fcvt.h.l        a0, a1
+       fcvt.h.l        a0, a1, rne
+       fcvt.h.lu       a0, a1
+       fcvt.h.lu       a0, a1, rne
+
+       fcvt.s.h        a0, a2
+       fcvt.d.h        a0, a2
+       fcvt.q.h        a0, a2
+       fcvt.h.s        a0, a2
+       fcvt.h.s        a0, a2, rne
+       fcvt.h.d        a0, a2
+       fcvt.h.d        a0, a2, rne
+       fcvt.h.q        a0, a2
+       fcvt.h.q        a0, a2, rne
+
+       fsgnj.h         a0, a1, a2
+       fsgnjn.h        a0, a1, a2
+       fsgnjx.h        a0, a1, a2
+       feq.h           a0, a1, a2
+       flt.h           a0, a1, a2
+       fle.h           a0, a1, a2
+       fgt.h           a0, a2, a1
+       fge.h           a0, a2, a1
+       fmv.h           a0, a1
+       fneg.h          a0, a1
+       fabs.h          a0, a1
+       fclass.h        a0, a1

diff --git a/include/opcode/riscv.h b/include/opcode/riscv.h
index 808f05f3d7a846d204b4993f3ba3fa670a5f2308..b115e338a05b9f0b2ff0825a68477cfe30a79817 100644 (file)
--- a/include/opcode/riscv.h
+++ b/include/opcode/riscv.h
@@ -370,10 +370,11 @@ enum riscv_insn_class
   INSN_CLASS_F_OR_ZFINX,
   INSN_CLASS_D_OR_ZDINX,
   INSN_CLASS_Q_OR_ZQINX,
-  INSN_CLASS_ZFH,
   INSN_CLASS_ZFH_OR_ZHINX,
-  INSN_CLASS_D_AND_ZFH_INX,
-  INSN_CLASS_Q_AND_ZFH_INX,
+  INSN_CLASS_ZFHMIN,
+  INSN_CLASS_ZFHMIN_OR_ZHINXMIN,
+  INSN_CLASS_ZFHMIN_AND_D,
+  INSN_CLASS_ZFHMIN_AND_Q,
   INSN_CLASS_ZBA,
   INSN_CLASS_ZBB,
   INSN_CLASS_ZBC,

diff --git a/opcodes/riscv-opc.c b/opcodes/riscv-opc.c
index d5cedbe176c5e1dbcde40cae35f26461e98ecd0f..2f9945aa93009bd9dc3e12b1fe2b8976c392163b 100644 (file)
--- a/opcodes/riscv-opc.c
+++ b/opcodes/riscv-opc.c
@@ -573,69 +573,69 @@ const struct riscv_opcode riscv_opcodes[] =
 {"remuw",     64, INSN_CLASS_M,   "d,s,t",     MATCH_REMUW, MASK_REMUW, match_opcode, 0 },
 
 /* Half-precision floating-point instruction subset.  */
-{"flh",        0, INSN_CLASS_ZFH,  "D,o(s)",    MATCH_FLH, MASK_FLH, match_opcode, INSN_DREF|INSN_2_BYTE },
-{"flh",        0, INSN_CLASS_ZFH,  "D,A,s",     0, (int) M_FLH, match_never, INSN_MACRO },
-{"fsh",        0, INSN_CLASS_ZFH,  "T,q(s)",    MATCH_FSH, MASK_FSH, match_opcode, INSN_DREF|INSN_2_BYTE },
-{"fsh",        0, INSN_CLASS_ZFH,  "T,A,s",     0, (int) M_FSH, match_never, INSN_MACRO },
-{"fmv.h",      0, INSN_CLASS_ZFH,  "D,U",       MATCH_FSGNJ_H, MASK_FSGNJ_H, match_rs1_eq_rs2, INSN_ALIAS },
-{"fneg.h",     0, INSN_CLASS_ZFH_OR_ZHINX,  "D,U",       MATCH_FSGNJN_H, MASK_FSGNJN_H, match_rs1_eq_rs2, INSN_ALIAS },
-{"fabs.h",     0, INSN_CLASS_ZFH_OR_ZHINX,  "D,U",       MATCH_FSGNJX_H, MASK_FSGNJX_H, match_rs1_eq_rs2, INSN_ALIAS },
-{"fsgnj.h",    0, INSN_CLASS_ZFH_OR_ZHINX,  "D,S,T",     MATCH_FSGNJ_H, MASK_FSGNJ_H, match_opcode, 0 },
-{"fsgnjn.h",   0, INSN_CLASS_ZFH_OR_ZHINX,  "D,S,T",     MATCH_FSGNJN_H, MASK_FSGNJN_H, match_opcode, 0 },
-{"fsgnjx.h",   0, INSN_CLASS_ZFH_OR_ZHINX,  "D,S,T",     MATCH_FSGNJX_H, MASK_FSGNJX_H, match_opcode, 0 },
-{"fadd.h",     0, INSN_CLASS_ZFH_OR_ZHINX,  "D,S,T",     MATCH_FADD_H|MASK_RM, MASK_FADD_H|MASK_RM, match_opcode, 0 },
-{"fadd.h",     0, INSN_CLASS_ZFH_OR_ZHINX,  "D,S,T,m",   MATCH_FADD_H, MASK_FADD_H, match_opcode, 0 },
-{"fsub.h",     0, INSN_CLASS_ZFH_OR_ZHINX,  "D,S,T",     MATCH_FSUB_H|MASK_RM, MASK_FSUB_H|MASK_RM, match_opcode, 0 },
-{"fsub.h",     0, INSN_CLASS_ZFH_OR_ZHINX,  "D,S,T,m",   MATCH_FSUB_H, MASK_FSUB_H, match_opcode, 0 },
-{"fmul.h",     0, INSN_CLASS_ZFH_OR_ZHINX,  "D,S,T",     MATCH_FMUL_H|MASK_RM, MASK_FMUL_H|MASK_RM, match_opcode, 0 },
-{"fmul.h",     0, INSN_CLASS_ZFH_OR_ZHINX,  "D,S,T,m",   MATCH_FMUL_H, MASK_FMUL_H, match_opcode, 0 },
-{"fdiv.h",     0, INSN_CLASS_ZFH_OR_ZHINX,  "D,S,T",     MATCH_FDIV_H|MASK_RM, MASK_FDIV_H|MASK_RM, match_opcode, 0 },
-{"fdiv.h",     0, INSN_CLASS_ZFH_OR_ZHINX,  "D,S,T,m",   MATCH_FDIV_H, MASK_FDIV_H, match_opcode, 0 },
-{"fsqrt.h",    0, INSN_CLASS_ZFH_OR_ZHINX,  "D,S",       MATCH_FSQRT_H|MASK_RM, MASK_FSQRT_H|MASK_RM, match_opcode, 0 },
-{"fsqrt.h",    0, INSN_CLASS_ZFH_OR_ZHINX,  "D,S,m",     MATCH_FSQRT_H, MASK_FSQRT_H, match_opcode, 0 },
-{"fmin.h",     0, INSN_CLASS_ZFH_OR_ZHINX,  "D,S,T",     MATCH_FMIN_H, MASK_FMIN_H, match_opcode, 0 },
-{"fmax.h",     0, INSN_CLASS_ZFH_OR_ZHINX,  "D,S,T",     MATCH_FMAX_H, MASK_FMAX_H, match_opcode, 0 },
-{"fmadd.h",    0, INSN_CLASS_ZFH_OR_ZHINX,  "D,S,T,R",   MATCH_FMADD_H|MASK_RM, MASK_FMADD_H|MASK_RM, match_opcode, 0 },
-{"fmadd.h",    0, INSN_CLASS_ZFH_OR_ZHINX,  "D,S,T,R,m", MATCH_FMADD_H, MASK_FMADD_H, match_opcode, 0 },
-{"fnmadd.h",   0, INSN_CLASS_ZFH_OR_ZHINX,  "D,S,T,R",   MATCH_FNMADD_H|MASK_RM, MASK_FNMADD_H|MASK_RM, match_opcode, 0 },
-{"fnmadd.h",   0, INSN_CLASS_ZFH_OR_ZHINX,  "D,S,T,R,m", MATCH_FNMADD_H, MASK_FNMADD_H, match_opcode, 0 },
-{"fmsub.h",    0, INSN_CLASS_ZFH_OR_ZHINX,  "D,S,T,R",   MATCH_FMSUB_H|MASK_RM, MASK_FMSUB_H|MASK_RM, match_opcode, 0 },
-{"fmsub.h",    0, INSN_CLASS_ZFH_OR_ZHINX,  "D,S,T,R,m", MATCH_FMSUB_H, MASK_FMSUB_H, match_opcode, 0 },
-{"fnmsub.h",   0, INSN_CLASS_ZFH_OR_ZHINX,  "D,S,T,R",   MATCH_FNMSUB_H|MASK_RM, MASK_FNMSUB_H|MASK_RM, match_opcode, 0 },
-{"fnmsub.h",   0, INSN_CLASS_ZFH_OR_ZHINX,  "D,S,T,R,m", MATCH_FNMSUB_H, MASK_FNMSUB_H, match_opcode, 0 },
-{"fcvt.w.h",   0, INSN_CLASS_ZFH_OR_ZHINX,  "d,S",       MATCH_FCVT_W_H|MASK_RM, MASK_FCVT_W_H|MASK_RM, match_opcode, 0 },
-{"fcvt.w.h",   0, INSN_CLASS_ZFH_OR_ZHINX,  "d,S,m",     MATCH_FCVT_W_H, MASK_FCVT_W_H, match_opcode, 0 },
-{"fcvt.wu.h",  0, INSN_CLASS_ZFH_OR_ZHINX,  "d,S",       MATCH_FCVT_WU_H|MASK_RM, MASK_FCVT_WU_H|MASK_RM, match_opcode, 0 },
-{"fcvt.wu.h",  0, INSN_CLASS_ZFH_OR_ZHINX,  "d,S,m",     MATCH_FCVT_WU_H, MASK_FCVT_WU_H, match_opcode, 0 },
-{"fcvt.h.w",   0, INSN_CLASS_ZFH_OR_ZHINX,  "D,s",       MATCH_FCVT_H_W|MASK_RM, MASK_FCVT_H_W|MASK_RM, match_opcode, 0 },
-{"fcvt.h.w",   0, INSN_CLASS_ZFH_OR_ZHINX,  "D,s,m",     MATCH_FCVT_H_W, MASK_FCVT_H_W, match_opcode, 0 },
-{"fcvt.h.wu",  0, INSN_CLASS_ZFH_OR_ZHINX,  "D,s",       MATCH_FCVT_H_WU|MASK_RM, MASK_FCVT_H_WU|MASK_RM, match_opcode, 0 },
-{"fcvt.h.wu",  0, INSN_CLASS_ZFH_OR_ZHINX,  "D,s,m",     MATCH_FCVT_H_WU, MASK_FCVT_H_WU, match_opcode, 0 },
-{"fcvt.s.h",   0, INSN_CLASS_ZFH_OR_ZHINX,  "D,S",       MATCH_FCVT_S_H, MASK_FCVT_S_H|MASK_RM, match_opcode, 0 },
-{"fcvt.d.h",   0, INSN_CLASS_D_AND_ZFH_INX,  "D,S",       MATCH_FCVT_D_H, MASK_FCVT_D_H|MASK_RM, match_opcode, 0 },
-{"fcvt.q.h",   0, INSN_CLASS_Q_AND_ZFH_INX,  "D,S",       MATCH_FCVT_Q_H, MASK_FCVT_Q_H|MASK_RM, match_opcode, 0 },
-{"fcvt.h.s",   0, INSN_CLASS_ZFH_OR_ZHINX,  "D,S",       MATCH_FCVT_H_S|MASK_RM, MASK_FCVT_H_S|MASK_RM, match_opcode, 0 },
-{"fcvt.h.s",   0, INSN_CLASS_ZFH_OR_ZHINX,  "D,S,m",     MATCH_FCVT_H_S, MASK_FCVT_H_S, match_opcode, 0 },
-{"fcvt.h.d",   0, INSN_CLASS_D_AND_ZFH_INX,  "D,S",       MATCH_FCVT_H_D|MASK_RM, MASK_FCVT_H_D|MASK_RM, match_opcode, 0 },
-{"fcvt.h.d",   0, INSN_CLASS_D_AND_ZFH_INX,  "D,S,m",     MATCH_FCVT_H_D, MASK_FCVT_H_D, match_opcode, 0 },
-{"fcvt.h.q",   0, INSN_CLASS_Q_AND_ZFH_INX,  "D,S",       MATCH_FCVT_H_Q|MASK_RM, MASK_FCVT_H_Q|MASK_RM, match_opcode, 0 },
-{"fcvt.h.q",   0, INSN_CLASS_Q_AND_ZFH_INX,  "D,S,m",     MATCH_FCVT_H_Q, MASK_FCVT_H_Q, match_opcode, 0 },
-{"fclass.h",   0, INSN_CLASS_ZFH_OR_ZHINX,  "d,S",       MATCH_FCLASS_H, MASK_FCLASS_H, match_opcode, 0 },
-{"feq.h",      0, INSN_CLASS_ZFH_OR_ZHINX,  "d,S,T",     MATCH_FEQ_H, MASK_FEQ_H, match_opcode, 0 },
-{"flt.h",      0, INSN_CLASS_ZFH_OR_ZHINX,  "d,S,T",     MATCH_FLT_H, MASK_FLT_H, match_opcode, 0 },
-{"fle.h",      0, INSN_CLASS_ZFH_OR_ZHINX,  "d,S,T",     MATCH_FLE_H, MASK_FLE_H, match_opcode, 0 },
-{"fgt.h",      0, INSN_CLASS_ZFH_OR_ZHINX,  "d,T,S",     MATCH_FLT_H, MASK_FLT_H, match_opcode, 0 },
-{"fge.h",      0, INSN_CLASS_ZFH_OR_ZHINX,  "d,T,S",     MATCH_FLE_H, MASK_FLE_H, match_opcode, 0 },
-{"fmv.x.h",    0, INSN_CLASS_ZFH,  "d,S",       MATCH_FMV_X_H, MASK_FMV_X_H, match_opcode, 0 },
-{"fmv.h.x",    0, INSN_CLASS_ZFH,  "D,s",       MATCH_FMV_H_X, MASK_FMV_H_X, match_opcode, 0 },
-{"fcvt.l.h",  64, INSN_CLASS_ZFH_OR_ZHINX,  "d,S",       MATCH_FCVT_L_H|MASK_RM, MASK_FCVT_L_H|MASK_RM, match_opcode, 0 },
-{"fcvt.l.h",  64, INSN_CLASS_ZFH_OR_ZHINX,  "d,S,m",     MATCH_FCVT_L_H, MASK_FCVT_L_H, match_opcode, 0 },
-{"fcvt.lu.h", 64, INSN_CLASS_ZFH_OR_ZHINX,  "d,S",       MATCH_FCVT_LU_H|MASK_RM, MASK_FCVT_LU_H|MASK_RM, match_opcode, 0 },
-{"fcvt.lu.h", 64, INSN_CLASS_ZFH_OR_ZHINX,  "d,S,m",     MATCH_FCVT_LU_H, MASK_FCVT_LU_H, match_opcode, 0 },
-{"fcvt.h.l",  64, INSN_CLASS_ZFH_OR_ZHINX,  "D,s",       MATCH_FCVT_H_L|MASK_RM, MASK_FCVT_H_L|MASK_RM, match_opcode, 0 },
-{"fcvt.h.l",  64, INSN_CLASS_ZFH_OR_ZHINX,  "D,s,m",     MATCH_FCVT_H_L, MASK_FCVT_H_L, match_opcode, 0 },
-{"fcvt.h.lu", 64, INSN_CLASS_ZFH_OR_ZHINX,  "D,s",       MATCH_FCVT_H_LU|MASK_RM, MASK_FCVT_H_L|MASK_RM, match_opcode, 0 },
-{"fcvt.h.lu", 64, INSN_CLASS_ZFH_OR_ZHINX,  "D,s,m",     MATCH_FCVT_H_LU, MASK_FCVT_H_LU, match_opcode, 0 },
+{"flh",        0, INSN_CLASS_ZFHMIN,   "D,o(s)",    MATCH_FLH, MASK_FLH, match_opcode, INSN_DREF|INSN_2_BYTE },
+{"flh",        0, INSN_CLASS_ZFHMIN,   "D,A,s",     0, (int) M_FLH, match_never, INSN_MACRO },
+{"fsh",        0, INSN_CLASS_ZFHMIN,   "T,q(s)",    MATCH_FSH, MASK_FSH, match_opcode, INSN_DREF|INSN_2_BYTE },
+{"fsh",        0, INSN_CLASS_ZFHMIN,   "T,A,s",     0, (int) M_FSH, match_never, INSN_MACRO },
+{"fmv.x.h",    0, INSN_CLASS_ZFHMIN,   "d,S",       MATCH_FMV_X_H, MASK_FMV_X_H, match_opcode, 0 },
+{"fmv.h.x",    0, INSN_CLASS_ZFHMIN,   "D,s",       MATCH_FMV_H_X, MASK_FMV_H_X, match_opcode, 0 },
+{"fmv.h",      0, INSN_CLASS_ZFH_OR_ZHINX,   "D,U",       MATCH_FSGNJ_H, MASK_FSGNJ_H, match_rs1_eq_rs2, INSN_ALIAS },
+{"fneg.h",     0, INSN_CLASS_ZFH_OR_ZHINX,   "D,U",       MATCH_FSGNJN_H, MASK_FSGNJN_H, match_rs1_eq_rs2, INSN_ALIAS },
+{"fabs.h",     0, INSN_CLASS_ZFH_OR_ZHINX,   "D,U",       MATCH_FSGNJX_H, MASK_FSGNJX_H, match_rs1_eq_rs2, INSN_ALIAS },
+{"fsgnj.h",    0, INSN_CLASS_ZFH_OR_ZHINX,   "D,S,T",     MATCH_FSGNJ_H, MASK_FSGNJ_H, match_opcode, 0 },
+{"fsgnjn.h",   0, INSN_CLASS_ZFH_OR_ZHINX,   "D,S,T",     MATCH_FSGNJN_H, MASK_FSGNJN_H, match_opcode, 0 },
+{"fsgnjx.h",   0, INSN_CLASS_ZFH_OR_ZHINX,   "D,S,T",     MATCH_FSGNJX_H, MASK_FSGNJX_H, match_opcode, 0 },
+{"fadd.h",     0, INSN_CLASS_ZFH_OR_ZHINX,   "D,S,T",     MATCH_FADD_H|MASK_RM, MASK_FADD_H|MASK_RM, match_opcode, 0 },
+{"fadd.h",     0, INSN_CLASS_ZFH_OR_ZHINX,   "D,S,T,m",   MATCH_FADD_H, MASK_FADD_H, match_opcode, 0 },
+{"fsub.h",     0, INSN_CLASS_ZFH_OR_ZHINX,   "D,S,T",     MATCH_FSUB_H|MASK_RM, MASK_FSUB_H|MASK_RM, match_opcode, 0 },
+{"fsub.h",     0, INSN_CLASS_ZFH_OR_ZHINX,   "D,S,T,m",   MATCH_FSUB_H, MASK_FSUB_H, match_opcode, 0 },
+{"fmul.h",     0, INSN_CLASS_ZFH_OR_ZHINX,   "D,S,T",     MATCH_FMUL_H|MASK_RM, MASK_FMUL_H|MASK_RM, match_opcode, 0 },
+{"fmul.h",     0, INSN_CLASS_ZFH_OR_ZHINX,   "D,S,T,m",   MATCH_FMUL_H, MASK_FMUL_H, match_opcode, 0 },
+{"fdiv.h",     0, INSN_CLASS_ZFH_OR_ZHINX,   "D,S,T",     MATCH_FDIV_H|MASK_RM, MASK_FDIV_H|MASK_RM, match_opcode, 0 },
+{"fdiv.h",     0, INSN_CLASS_ZFH_OR_ZHINX,   "D,S,T,m",   MATCH_FDIV_H, MASK_FDIV_H, match_opcode, 0 },
+{"fsqrt.h",    0, INSN_CLASS_ZFH_OR_ZHINX,   "D,S",       MATCH_FSQRT_H|MASK_RM, MASK_FSQRT_H|MASK_RM, match_opcode, 0 },
+{"fsqrt.h",    0, INSN_CLASS_ZFH_OR_ZHINX,   "D,S,m",     MATCH_FSQRT_H, MASK_FSQRT_H, match_opcode, 0 },
+{"fmin.h",     0, INSN_CLASS_ZFH_OR_ZHINX,   "D,S,T",     MATCH_FMIN_H, MASK_FMIN_H, match_opcode, 0 },
+{"fmax.h",     0, INSN_CLASS_ZFH_OR_ZHINX,   "D,S,T",     MATCH_FMAX_H, MASK_FMAX_H, match_opcode, 0 },
+{"fmadd.h",    0, INSN_CLASS_ZFH_OR_ZHINX,   "D,S,T,R",   MATCH_FMADD_H|MASK_RM, MASK_FMADD_H|MASK_RM, match_opcode, 0 },
+{"fmadd.h",    0, INSN_CLASS_ZFH_OR_ZHINX,   "D,S,T,R,m", MATCH_FMADD_H, MASK_FMADD_H, match_opcode, 0 },
+{"fnmadd.h",   0, INSN_CLASS_ZFH_OR_ZHINX,   "D,S,T,R",   MATCH_FNMADD_H|MASK_RM, MASK_FNMADD_H|MASK_RM, match_opcode, 0 },
+{"fnmadd.h",   0, INSN_CLASS_ZFH_OR_ZHINX,   "D,S,T,R,m", MATCH_FNMADD_H, MASK_FNMADD_H, match_opcode, 0 },
+{"fmsub.h",    0, INSN_CLASS_ZFH_OR_ZHINX,   "D,S,T,R",   MATCH_FMSUB_H|MASK_RM, MASK_FMSUB_H|MASK_RM, match_opcode, 0 },
+{"fmsub.h",    0, INSN_CLASS_ZFH_OR_ZHINX,   "D,S,T,R,m", MATCH_FMSUB_H, MASK_FMSUB_H, match_opcode, 0 },
+{"fnmsub.h",   0, INSN_CLASS_ZFH_OR_ZHINX,   "D,S,T,R",   MATCH_FNMSUB_H|MASK_RM, MASK_FNMSUB_H|MASK_RM, match_opcode, 0 },
+{"fnmsub.h",   0, INSN_CLASS_ZFH_OR_ZHINX,   "D,S,T,R,m", MATCH_FNMSUB_H, MASK_FNMSUB_H, match_opcode, 0 },
+{"fcvt.w.h",   0, INSN_CLASS_ZFH_OR_ZHINX,   "d,S",       MATCH_FCVT_W_H|MASK_RM, MASK_FCVT_W_H|MASK_RM, match_opcode, 0 },
+{"fcvt.w.h",   0, INSN_CLASS_ZFH_OR_ZHINX,   "d,S,m",     MATCH_FCVT_W_H, MASK_FCVT_W_H, match_opcode, 0 },
+{"fcvt.wu.h",  0, INSN_CLASS_ZFH_OR_ZHINX,   "d,S",       MATCH_FCVT_WU_H|MASK_RM, MASK_FCVT_WU_H|MASK_RM, match_opcode, 0 },
+{"fcvt.wu.h",  0, INSN_CLASS_ZFH_OR_ZHINX,   "d,S,m",     MATCH_FCVT_WU_H, MASK_FCVT_WU_H, match_opcode, 0 },
+{"fcvt.h.w",   0, INSN_CLASS_ZFH_OR_ZHINX,   "D,s",       MATCH_FCVT_H_W|MASK_RM, MASK_FCVT_H_W|MASK_RM, match_opcode, 0 },
+{"fcvt.h.w",   0, INSN_CLASS_ZFH_OR_ZHINX,   "D,s,m",     MATCH_FCVT_H_W, MASK_FCVT_H_W, match_opcode, 0 },
+{"fcvt.h.wu",  0, INSN_CLASS_ZFH_OR_ZHINX,   "D,s",       MATCH_FCVT_H_WU|MASK_RM, MASK_FCVT_H_WU|MASK_RM, match_opcode, 0 },
+{"fcvt.h.wu",  0, INSN_CLASS_ZFH_OR_ZHINX,   "D,s,m",     MATCH_FCVT_H_WU, MASK_FCVT_H_WU, match_opcode, 0 },
+{"fcvt.s.h",   0, INSN_CLASS_ZFHMIN_OR_ZHINXMIN, "D,S",     MATCH_FCVT_S_H, MASK_FCVT_S_H|MASK_RM, match_opcode, 0 },
+{"fcvt.d.h",   0, INSN_CLASS_ZFHMIN_AND_D,     "D,S",       MATCH_FCVT_D_H, MASK_FCVT_D_H|MASK_RM, match_opcode, 0 },
+{"fcvt.q.h",   0, INSN_CLASS_ZFHMIN_AND_Q,     "D,S",       MATCH_FCVT_Q_H, MASK_FCVT_Q_H|MASK_RM, match_opcode, 0 },
+{"fcvt.h.s",   0, INSN_CLASS_ZFHMIN_OR_ZHINXMIN, "D,S",     MATCH_FCVT_H_S|MASK_RM, MASK_FCVT_H_S|MASK_RM, match_opcode, 0 },
+{"fcvt.h.s",   0, INSN_CLASS_ZFHMIN_OR_ZHINXMIN, "D,S,m",   MATCH_FCVT_H_S, MASK_FCVT_H_S, match_opcode, 0 },
+{"fcvt.h.d",   0, INSN_CLASS_ZFHMIN_AND_D,     "D,S",       MATCH_FCVT_H_D|MASK_RM, MASK_FCVT_H_D|MASK_RM, match_opcode, 0 },
+{"fcvt.h.d",   0, INSN_CLASS_ZFHMIN_AND_D,     "D,S,m",     MATCH_FCVT_H_D, MASK_FCVT_H_D, match_opcode, 0 },
+{"fcvt.h.q",   0, INSN_CLASS_ZFHMIN_AND_Q,     "D,S",       MATCH_FCVT_H_Q|MASK_RM, MASK_FCVT_H_Q|MASK_RM, match_opcode, 0 },
+{"fcvt.h.q",   0, INSN_CLASS_ZFHMIN_AND_Q,     "D,S,m",     MATCH_FCVT_H_Q, MASK_FCVT_H_Q, match_opcode, 0 },
+{"fclass.h",   0, INSN_CLASS_ZFH_OR_ZHINX,   "d,S",       MATCH_FCLASS_H, MASK_FCLASS_H, match_opcode, 0 },
+{"feq.h",      0, INSN_CLASS_ZFH_OR_ZHINX,   "d,S,T",     MATCH_FEQ_H, MASK_FEQ_H, match_opcode, 0 },
+{"flt.h",      0, INSN_CLASS_ZFH_OR_ZHINX,   "d,S,T",     MATCH_FLT_H, MASK_FLT_H, match_opcode, 0 },
+{"fle.h",      0, INSN_CLASS_ZFH_OR_ZHINX,   "d,S,T",     MATCH_FLE_H, MASK_FLE_H, match_opcode, 0 },
+{"fgt.h",      0, INSN_CLASS_ZFH_OR_ZHINX,   "d,T,S",     MATCH_FLT_H, MASK_FLT_H, match_opcode, 0 },
+{"fge.h",      0, INSN_CLASS_ZFH_OR_ZHINX,   "d,T,S",     MATCH_FLE_H, MASK_FLE_H, match_opcode, 0 },
+{"fcvt.l.h",  64, INSN_CLASS_ZFH_OR_ZHINX,   "d,S",       MATCH_FCVT_L_H|MASK_RM, MASK_FCVT_L_H|MASK_RM, match_opcode, 0 },
+{"fcvt.l.h",  64, INSN_CLASS_ZFH_OR_ZHINX,   "d,S,m",     MATCH_FCVT_L_H, MASK_FCVT_L_H, match_opcode, 0 },
+{"fcvt.lu.h", 64, INSN_CLASS_ZFH_OR_ZHINX,   "d,S",       MATCH_FCVT_LU_H|MASK_RM, MASK_FCVT_LU_H|MASK_RM, match_opcode, 0 },
+{"fcvt.lu.h", 64, INSN_CLASS_ZFH_OR_ZHINX,   "d,S,m",     MATCH_FCVT_LU_H, MASK_FCVT_LU_H, match_opcode, 0 },
+{"fcvt.h.l",  64, INSN_CLASS_ZFH_OR_ZHINX,   "D,s",       MATCH_FCVT_H_L|MASK_RM, MASK_FCVT_H_L|MASK_RM, match_opcode, 0 },
+{"fcvt.h.l",  64, INSN_CLASS_ZFH_OR_ZHINX,   "D,s,m",     MATCH_FCVT_H_L, MASK_FCVT_H_L, match_opcode, 0 },
+{"fcvt.h.lu", 64, INSN_CLASS_ZFH_OR_ZHINX,   "D,s",       MATCH_FCVT_H_LU|MASK_RM, MASK_FCVT_H_LU|MASK_RM, match_opcode, 0 },
+{"fcvt.h.lu", 64, INSN_CLASS_ZFH_OR_ZHINX,   "D,s,m",     MATCH_FCVT_H_LU, MASK_FCVT_H_LU, match_opcode, 0 },
 
 /* Single-precision floating-point instruction subset.  */
 {"frcsr",      0, INSN_CLASS_F_OR_ZFINX,   "d",         MATCH_FRCSR, MASK_FRCSR, match_opcode, INSN_ALIAS },