No implicit conversion from IdString to anything else

diff --git a/backends/blif/blif.cc b/backends/blif/blif.cc
index ecde8b5a39183296b271451a39e742b1525a9f61..5daab6691c5cb377854f594206e68bddc69f76c6 100644 (file)
--- a/backends/blif/blif.cc
+++ b/backends/blif/blif.cc
@@ -363,7 +363,7 @@ struct BlifBackend : public Backend {
                if (top_module_name.empty())
                        for (auto & mod_it:design->modules_)
                                if (mod_it.second->get_bool_attribute("\\top"))
-                                       top_module_name = mod_it.first;
+                                       top_module_name = mod_it.first.str();
 
                fprintf(f, "# Generated by %s\n", yosys_version_str);
 

diff --git a/backends/btor/btor.cc b/backends/btor/btor.cc
index 201be0cf5fe8105a418fc424e95d6de18f241a65..a81d8f159b7441a9a76c3174cf0e00324f0b52aa 100644 (file)
--- a/backends/btor/btor.cc
+++ b/backends/btor/btor.cc
@@ -968,7 +968,7 @@ struct BtorBackend : public Backend {
                if (top_module_name.empty())
                        for (auto & mod_it:design->modules_)
                                if (mod_it.second->get_bool_attribute("\\top"))
-                                       top_module_name = mod_it.first;
+                                       top_module_name = mod_it.first.str();
 
                fprintf(f, "; Generated by %s\n", yosys_version_str);
                fprintf(f, ";  %s developed and maintained by Clifford Wolf <clifford@clifford.at>\n", yosys_version_str);

diff --git a/backends/edif/edif.cc b/backends/edif/edif.cc
index bf1efc4aeb71398748bf0de11194d70fdbf2a1ff..ecdfaabfc9de705276c43c23050340cbb9c8fafe 100644 (file)
--- a/backends/edif/edif.cc
+++ b/backends/edif/edif.cc
@@ -126,7 +126,7 @@ struct EdifBackend : public Backend {
                if (top_module_name.empty())
                        for (auto & mod_it:design->modules_)
                                if (mod_it.second->get_bool_attribute("\\top"))
-                                       top_module_name = mod_it.first;
+                                       top_module_name = mod_it.first.str();
 
                for (auto module_it : design->modules_)
                {
@@ -135,7 +135,7 @@ struct EdifBackend : public Backend {
                                continue;
 
                        if (top_module_name.empty())
-                               top_module_name = module->name;
+                               top_module_name = module->name.str();
 
                        if (module->processes.size() != 0)
                                log_error("Found unmapped processes in module %s: unmapped processes are not supported in EDIF backend!\n", RTLIL::id2cstr(module->name));

diff --git a/backends/spice/spice.cc b/backends/spice/spice.cc
index a445e9cc9059a763ae8161feedfd9d0b560b71d1..be0086ffd3fb5f7cb38ffe7af8bc6cbff65477bc 100644 (file)
--- a/backends/spice/spice.cc
+++ b/backends/spice/spice.cc
@@ -172,7 +172,7 @@ struct SpiceBackend : public Backend {
                if (top_module_name.empty())
                        for (auto & mod_it:design->modules_)
                                if (mod_it.second->get_bool_attribute("\\top"))
-                                       top_module_name = mod_it.first;
+                                       top_module_name = mod_it.first.str();
 
                fprintf(f, "* SPICE netlist generated by %s\n", yosys_version_str);
                fprintf(f, "\n");

diff --git a/kernel/log.cc b/kernel/log.cc
index 01f6207ec934c5bb39789aca2a4613e3489a5542..81cc26da38d35dfe6706256bb009804ca4176adb 100644 (file)
--- a/kernel/log.cc
+++ b/kernel/log.cc
@@ -215,7 +215,7 @@ const char *log_signal(const RTLIL::SigSpec &sig, bool autoint)
 
 const char *log_id(RTLIL::IdString str)
 {
-       const char *p = str;
+       const char *p = str.c_str();
        log_assert(RTLIL::IdString::global_refcount_storage_[str.index_] > 1);
        if (p[0] == '\\' && p[1] != '$' && p[1] != 0)
                return p+1;

diff --git a/kernel/register.cc b/kernel/register.cc
index 4d204069c3da768c4220405fe3486137a0290a37..868dbb9493f4af7f2928c993c72fa6dc404ba8c4 100644 (file)
--- a/kernel/register.cc
+++ b/kernel/register.cc
@@ -240,7 +240,7 @@ void Pass::call_on_selection(RTLIL::Design *design, const RTLIL::Selection &sele
 void Pass::call_on_module(RTLIL::Design *design, RTLIL::Module *module, std::string command)
 {
        std::string backup_selected_active_module = design->selected_active_module;
-       design->selected_active_module = module->name;
+       design->selected_active_module = module->name.str();
        design->selection_stack.push_back(RTLIL::Selection(false));
        design->selection_stack.back().select(module);
 
@@ -253,7 +253,7 @@ void Pass::call_on_module(RTLIL::Design *design, RTLIL::Module *module, std::str
 void Pass::call_on_module(RTLIL::Design *design, RTLIL::Module *module, std::vector<std::string> args)
 {
        std::string backup_selected_active_module = design->selected_active_module;
-       design->selected_active_module = module->name;
+       design->selected_active_module = module->name.str();
        design->selection_stack.push_back(RTLIL::Selection(false));
        design->selection_stack.back().select(module);
 

diff --git a/kernel/rtlil.cc b/kernel/rtlil.cc
index 9ee8123ffbb443c3a4dda7259b5734bf2d5658d9..2838449bbf68e1c2b991f10e2324a15d479ff18f 100644 (file)
--- a/kernel/rtlil.cc
+++ b/kernel/rtlil.cc
@@ -286,7 +286,7 @@ void RTLIL::Design::check()
        for (auto &it : modules_) {
                log_assert(this == it.second->design);
                log_assert(it.first == it.second->name);
-               log_assert(it.first.size() > 0 && (it.first[0] == '\\' || it.first[0] == '$'));
+               log_assert(!it.first.empty());
                it.second->check();
        }
 #endif
@@ -499,7 +499,7 @@ namespace {
 
                void check()
                {
-                       if (cell->type[0] != '$' || cell->type.substr(0, 3) == "$__" || cell->type.substr(0, 8) == "$paramod" ||
+                       if (cell->type.substr(0, 1) != "$" || cell->type.substr(0, 3) == "$__" || cell->type.substr(0, 8) == "$paramod" ||
                                        cell->type.substr(0, 9) == "$verific$" || cell->type.substr(0, 7) == "$array:" || cell->type.substr(0, 8) == "$extern:")
                                return;
 
@@ -818,38 +818,38 @@ void RTLIL::Module::check()
        for (auto &it : wires_) {
                log_assert(this == it.second->module);
                log_assert(it.first == it.second->name);
-               log_assert(it.first.size() > 0 && (it.first[0] == '\\' || it.first[0] == '$'));
+               log_assert(!it.first.empty());
                log_assert(it.second->width >= 0);
                log_assert(it.second->port_id >= 0);
                for (auto &it2 : it.second->attributes) {
-                       log_assert(it2.first.size() > 0 && (it2.first[0] == '\\' || it2.first[0] == '$'));
+                       log_assert(!it2.first.empty());
                }
        }
 
        for (auto &it : memories) {
                log_assert(it.first == it.second->name);
-               log_assert(it.first.size() > 0 && (it.first[0] == '\\' || it.first[0] == '$'));
+               log_assert(!it.first.empty());
                log_assert(it.second->width >= 0);
                log_assert(it.second->size >= 0);
                for (auto &it2 : it.second->attributes) {
-                       log_assert(it2.first.size() > 0 && (it2.first[0] == '\\' || it2.first[0] == '$'));
+                       log_assert(!it2.first.empty());
                }
        }
 
        for (auto &it : cells_) {
                log_assert(this == it.second->module);
                log_assert(it.first == it.second->name);
-               log_assert(it.first.size() > 0 && (it.first[0] == '\\' || it.first[0] == '$'));
-               log_assert(it.second->type.size() > 0 && (it.second->type[0] == '\\' || it.second->type[0] == '$'));
+               log_assert(!it.first.empty());
+               log_assert(!it.second->type.empty());
                for (auto &it2 : it.second->connections()) {
-                       log_assert(it2.first.size() > 0 && (it2.first[0] == '\\' || it2.first[0] == '$'));
+                       log_assert(!it2.first.empty());
                        it2.second.check();
                }
                for (auto &it2 : it.second->attributes) {
-                       log_assert(it2.first.size() > 0 && (it2.first[0] == '\\' || it2.first[0] == '$'));
+                       log_assert(!it2.first.empty());
                }
                for (auto &it2 : it.second->parameters) {
-                       log_assert(it2.first.size() > 0 && (it2.first[0] == '\\' || it2.first[0] == '$'));
+                       log_assert(!it2.first.empty());
                }
                InternalCellChecker checker(this, it.second);
                checker.check();
@@ -857,7 +857,7 @@ void RTLIL::Module::check()
 
        for (auto &it : processes) {
                log_assert(it.first == it.second->name);
-               log_assert(it.first.size() > 0 && (it.first[0] == '\\' || it.first[0] == '$'));
+               log_assert(!it.first.empty());
                // FIXME: More checks here..
        }
 
@@ -868,7 +868,7 @@ void RTLIL::Module::check()
        }
 
        for (auto &it : attributes) {
-               log_assert(it.first.size() > 0 && (it.first[0] == '\\' || it.first[0] == '$'));
+               log_assert(!it.first.empty());
        }
 #endif
 }
@@ -1597,7 +1597,7 @@ void RTLIL::Cell::check()
 
 void RTLIL::Cell::fixup_parameters(bool set_a_signed, bool set_b_signed)
 {
-       if (type[0] != '$' || type.substr(0, 2) == "$_" || type.substr(0, 8) == "$paramod" ||
+       if (type.substr(0, 1) != "$" || type.substr(0, 2) == "$_" || type.substr(0, 8) == "$paramod" ||
                        type.substr(0, 9) == "$verific$" || type.substr(0, 7) == "$array:" || type.substr(0, 8) == "$extern:")
                return;
 

diff --git a/kernel/rtlil.h b/kernel/rtlil.h
index 6529603ebb1560d49b54a0ea2e56118aa01a9064..502969a1f01a6304f40efd14e193bc63dc38a79b 100644 (file)
--- a/kernel/rtlil.h
+++ b/kernel/rtlil.h
@@ -162,11 +162,7 @@ namespace RTLIL
                        *this = id;
                }
 
-               const char*c_str() const {
-                       return global_id_storage_.at(index_);
-               }
-
-               operator const char*() const {
+               const char *c_str() const {
                        return global_id_storage_.at(index_);
                }
 
@@ -193,6 +189,10 @@ namespace RTLIL
                        return c_str()[i];
                }
 
+               char operator[](size_t i) const {
+                       return c_str()[i];
+               }
+
                std::string substr(size_t pos = 0, size_t len = std::string::npos) const {
                        if (len == std::string::npos || len >= strlen(c_str() + pos))
                                return std::string(c_str() + pos);

diff --git a/passes/abc/abc.cc b/passes/abc/abc.cc
index 1966435788d47e63c3fc8ff2ff9c0d94bcd4d238..77419e6163d26d7b23c1670c2299a59644d1f301 100644 (file)
--- a/passes/abc/abc.cc
+++ b/passes/abc/abc.cc
@@ -303,7 +303,7 @@ static void handle_loops()
                                        id1 = id2;
                                else if (edges[id1].size() > edges[id2].size())
                                        continue;
-                               else if (w1->name > w2->name)
+                               else if (w2->name < w1->name)
                                        id1 = id2;
                        }
 

diff --git a/passes/cmds/design.cc b/passes/cmds/design.cc
index 260e7b5d9a09e3b3a309aec1e23945565ecd6e49..9f800c31f5ffd0f2fb150585f11ebfdcefca51d5 100644 (file)
--- a/passes/cmds/design.cc
+++ b/passes/cmds/design.cc
@@ -192,7 +192,7 @@ struct DesignPass : public Pass {
 
                        for (auto mod : copy_src_modules)
                        {
-                               std::string trg_name = as_name.empty() ? std::string(mod->name) : RTLIL::escape_id(as_name);
+                               std::string trg_name = as_name.empty() ? mod->name.str() : RTLIL::escape_id(as_name);
 
                                if (copy_to_design->modules_.count(trg_name))
                                        delete copy_to_design->modules_.at(trg_name);

diff --git a/passes/cmds/select.cc b/passes/cmds/select.cc
index b4f4d26ae5728636e5e6e44f71d83831280bde1b..2d49e85edf4b64e06aa0a7ee897779b993b9dff1 100644 (file)
--- a/passes/cmds/select.cc
+++ b/passes/cmds/select.cc
@@ -1080,7 +1080,7 @@ struct SelectPass : public Pass {
                                RTLIL::IdString mod_name = RTLIL::escape_id(args[++argidx]);
                                if (design->modules_.count(mod_name) == 0)
                                        log_cmd_error("No such module: %s\n", id2cstr(mod_name));
-                               design->selected_active_module = mod_name;
+                               design->selected_active_module = mod_name.str();
                                got_module = true;
                                continue;
                        }
@@ -1304,7 +1304,7 @@ struct CdPass : public Pass {
                        if (design->modules_.count(design->selected_active_module) > 0)
                                module = design->modules_.at(design->selected_active_module);
                        if (module != NULL && module->cells_.count(modname) > 0)
-                               modname = module->cells_.at(modname)->type;
+                               modname = module->cells_.at(modname)->type.str();
                }
 
                if (design->modules_.count(modname) > 0) {

diff --git a/passes/cmds/show.cc b/passes/cmds/show.cc
index bbc0ff44f87893bee0e8f648f193688887f9f7a2..cbc4725f7a29ef073c527b9853b1ae569ef82c18 100644 (file)
--- a/passes/cmds/show.cc
+++ b/passes/cmds/show.cc
@@ -322,7 +322,7 @@ struct ShowWorker
                                else if (it.second->port_output)
                                        all_sinks.insert(stringf("n%d", id2num(it.first)));
                        } else {
-                               wires_on_demand[stringf("n%d", id2num(it.first))] = it.first;
+                               wires_on_demand[stringf("n%d", id2num(it.first))] = it.first.str();
                        }
                }
 

diff --git a/passes/fsm/fsm_export.cc b/passes/fsm/fsm_export.cc
index 97ccf91ea2e11040027dac1f16cbbf26eeba1ef9..cb762dc1af8b0c016939f424c610fc64f9d061a6 100644 (file)
--- a/passes/fsm/fsm_export.cc
+++ b/passes/fsm/fsm_export.cc
@@ -61,7 +61,7 @@ void write_kiss2(struct RTLIL::Module *module, struct RTLIL::Cell *cell, std::st
                kiss_name.assign(attr_it->second.decode_string());
        }
        else {
-               kiss_name.assign(module->name);
+               kiss_name.assign(module->name.str());
                kiss_name.append('-' + cell->name.str() + ".kiss2");
        }
 

diff --git a/passes/memory/memory_collect.cc b/passes/memory/memory_collect.cc
index 471a7d53a06f9be80044d2c64b2e034f5a8fc92a..9c670f00ff68d0569335dfac26e5fa59264ffed0 100644 (file)
--- a/passes/memory/memory_collect.cc
+++ b/passes/memory/memory_collect.cc
@@ -126,7 +126,7 @@ static void handle_memory(RTLIL::Module *module, RTLIL::Memory *memory)
        }
 
        std::stringstream sstr;
-       sstr << "$mem$" << memory->name << "$" << (autoidx++);
+       sstr << "$mem$" << memory->name.str() << "$" << (autoidx++);
 
        RTLIL::Cell *mem = module->addCell(sstr.str(), "$mem");
        mem->parameters["\\MEMID"] = RTLIL::Const(memory->name.str());

diff --git a/passes/techmap/extract.cc b/passes/techmap/extract.cc
index 06af2923bd5547d2b34fb4ee0352e994752a7087..985d51e501a71c02b4825407c1cee004fcfb451b 100644 (file)
--- a/passes/techmap/extract.cc
+++ b/passes/techmap/extract.cc
@@ -240,8 +240,8 @@ namespace
 
                                        if (sig_bit_ref.count(bit) == 0) {
                                                bit_ref_t &bit_ref = sig_bit_ref[bit];
-                                               bit_ref.cell = cell->name;
-                                               bit_ref.port = conn.first;
+                                               bit_ref.cell = cell->name.str();
+                                               bit_ref.port = conn.first.str();
                                                bit_ref.bit = i;
                                        }
 

diff --git a/passes/techmap/techmap.cc b/passes/techmap/techmap.cc
index 374fa9bf29a6d82dca3a53967a04817f7c3ba96f..c639cc48d31e296fa85593d39a5bfc4c51515632 100644 (file)
--- a/passes/techmap/techmap.cc
+++ b/passes/techmap/techmap.cc
@@ -155,7 +155,7 @@ struct TechmapWorker
                if (!flatten_mode)
                        for (auto &it : tpl->cells_)
                                if (it.first == "\\_TECHMAP_REPLACE_") {
-                                       orig_cell_name = cell->name;
+                                       orig_cell_name = cell->name.str();
                                        module->rename(cell, stringf("$techmap%d", autoidx++) + cell->name.str());
                                        break;
                                }