[libre-riscv-dev] [Bug 196] Formal correctness proof needed for the IEEE754 FPU

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+Date: Mon, 27 Apr 2020 20:44:56 +0000
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+X-Bugzilla-Product: Libre-SOC's first SoC
+X-Bugzilla-Component: Formal Verification
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+X-Bugzilla-Severity: enhancement
+X-Bugzilla-Who: lkcl@lkcl.net
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+Message-ID: <bug-196-13-9Edgrb4VDv@https.bugs.libre-soc.org/>
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+Subject: [libre-riscv-dev] [Bug 196] Formal correctness proof needed for the
+ IEEE754 FPU
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