Fixed the bitfield FCN to include the right bits.

--HG--
extra : convert_revision : 040beb4dd982784773c3c3ad04cc48c2dc98b58c

diff --git a/src/arch/sparc/isa/bitfields.isa b/src/arch/sparc/isa/bitfields.isa
index 372f5c4ef2167debf96ef77cc16dad1f909b0c47..7e884866c94a193174289203eaec2111d923bc3d 100644 (file)
--- a/src/arch/sparc/isa/bitfields.isa
+++ b/src/arch/sparc/isa/bitfields.isa
@@ -50,7 +50,7 @@ def bitfield D16LO    <13:0>;
 def bitfield DISP19    <18:0>;
 def bitfield DISP22    <21:0>;
 def bitfield DISP30    <29:0>;
-def bitfield FCN       <29:26>;
+def bitfield FCN       <29:25>;
 def bitfield I         <13>;
 def bitfield IMM_ASI   <12:5>;
 def bitfield IMM22     <21:0>;