//iris_batchbuffer_flush(...)
ice->state.dirty &= ~IRIS_DIRTY_STATE_BASE_ADDRESS;
-
+
/* XXX: PIPE_CONTROLs */
iris_emit_cmd(batch, GENX(STATE_BASE_ADDRESS), sba) {
{
const uint64_t dirty = ice->state.dirty;
- if (dirty & IRIS_DIRTY_URB) {
- }
-
- if (dirty & IRIS_DIRTY_WM_DEPTH_STENCIL) {
- struct iris_depth_stencil_alpha_state *cso = ice->state.cso_zsa;
- struct pipe_stencil_ref *p_stencil_refs = &ice->state.stencil_ref;
-
- uint32_t stencil_refs[GENX(3DSTATE_WM_DEPTH_STENCIL_length)];
- iris_pack_command(GENX(3DSTATE_WM_DEPTH_STENCIL), &stencil_refs, wmds) {
- wmds.StencilReferenceValue = p_stencil_refs->ref_value[0];
- wmds.BackfaceStencilReferenceValue = p_stencil_refs->ref_value[1];
- }
- iris_emit_merge(batch, cso->wmds, stencil_refs, ARRAY_SIZE(cso->wmds));
- }
-
if (dirty & IRIS_DIRTY_CC_VIEWPORT) {
struct iris_depth_stencil_alpha_state *cso = ice->state.cso_zsa;
iris_emit_cmd(batch, GENX(3DSTATE_VIEWPORT_STATE_POINTERS_CC), ptr) {
}
}
- if (dirty & IRIS_DIRTY_PS_BLEND) {
- struct iris_blend_state *cso = ice->state.cso_blend;
- iris_batch_emit(batch, cso->ps_blend, sizeof(cso->ps_blend));
- }
-
- if (dirty & IRIS_DIRTY_BLEND_STATE) {
- //struct iris_blend_state *cso = ice->state.cso_blend;
- // XXX: 3DSTATE_BLEND_STATE_POINTERS - BLEND_STATE
- // -> from iris_blend_state (most) + iris_depth_stencil_alpha_state
- // (alpha test function/enable) + has writeable RT from ???????
- }
-
if (dirty & IRIS_DIRTY_SF_CL_VIEWPORT) {
struct iris_viewport_state *cso = ice->state.cso_vp;
iris_emit_cmd(batch, GENX(3DSTATE_VIEWPORT_STATE_POINTERS_SF_CLIP), ptr) {
}
}
- if (dirty & IRIS_DIRTY_CLIP) {
- struct iris_rasterizer_state *cso = ice->state.cso_rast;
-
- uint32_t dynamic_clip[GENX(3DSTATE_CLIP_length)];
- iris_pack_command(GENX(3DSTATE_CLIP), &dynamic_clip, cl) {
- //.NonPerspectiveBarycentricEnable = <comes from FS prog> :(
- //.ForceZeroRTAIndexEnable = <comes from FB layers being 0>
- // also userclip stuffs...
- }
- iris_emit_merge(batch, cso->clip, dynamic_clip, ARRAY_SIZE(cso->clip));
- }
-
- if (dirty & IRIS_DIRTY_RASTER) {
- struct iris_rasterizer_state *cso = ice->state.cso_rast;
- iris_batch_emit(batch, cso->raster, sizeof(cso->raster));
- iris_batch_emit(batch, cso->sf, sizeof(cso->sf));
- }
+ /* XXX: L3 State */
- if (dirty & IRIS_DIRTY_LINE_STIPPLE) {
- struct iris_rasterizer_state *cso = ice->state.cso_rast;
- iris_batch_emit(batch, cso->line_stipple, sizeof(cso->line_stipple));
- }
-
- if (dirty & IRIS_DIRTY_SCISSOR) {
- uint32_t scissor_offset =
- iris_emit_state(batch, ice->state.scissors,
- sizeof(struct pipe_scissor_state) *
- ice->state.num_scissors, 32);
-
- iris_emit_cmd(batch, GENX(3DSTATE_SCISSOR_STATE_POINTERS), ptr) {
- ptr.ScissorRectPointer = scissor_offset;
- }
+ if (dirty & IRIS_DIRTY_URB) {
+ /* XXX: URB */
}
- if (dirty & IRIS_DIRTY_POLYGON_STIPPLE) {
- iris_emit_cmd(batch, GENX(3DSTATE_POLY_STIPPLE_PATTERN), poly) {
- for (int i = 0; i < 32; i++) {
- poly.PatternRow[i] = ice->state.poly_stipple.stipple[i];
- }
- }
+ if (dirty & IRIS_DIRTY_BLEND_STATE) {
+ //struct iris_blend_state *cso = ice->state.cso_blend;
+ // XXX: 3DSTATE_BLEND_STATE_POINTERS - BLEND_STATE
+ // -> from iris_blend_state (most) + iris_depth_stencil_alpha_state
+ // (alpha test function/enable) + has writeable RT from ???????
}
if (dirty & IRIS_DIRTY_COLOR_CALC_STATE) {
}
}
- if (dirty & IRIS_DIRTY_VERTEX_BUFFERS) {
- struct iris_vertex_buffer_state *cso = ice->state.cso_vertex_buffers;
+ // XXX: 3DSTATE_CONSTANT_XS
+ // XXX: 3DSTATE_BINDING_TABLE_POINTERS_XS
- STATIC_ASSERT(GENX(VERTEX_BUFFER_STATE_length) == 4);
- STATIC_ASSERT((GENX(VERTEX_BUFFER_STATE_BufferStartingAddress_bits) % 32) == 0);
+ for (int stage = 0; stage <= MESA_SHADER_FRAGMENT; stage++) {
+ if (!(dirty & (IRIS_DIRTY_SAMPLER_STATES_VS << stage)))
+ continue;
- uint64_t *addr = batch->cmdbuf.map_next + sizeof(uint32_t) *
- (GENX(VERTEX_BUFFER_STATE_BufferStartingAddress_bits) / 32);
- uint32_t *delta = cso->vertex_buffers +
- (1 + GENX(VERTEX_BUFFER_STATE_BufferStartingAddress_bits) / 32);
+ // XXX: get sampler count from shader; don't emit them all...
+ const int count = IRIS_MAX_TEXTURE_SAMPLERS;
- iris_batch_emit(batch, cso->vertex_buffers,
- sizeof(uint32_t) * (1 + 4 * cso->num_buffers));
+ uint32_t offset;
+ uint32_t *map = iris_alloc_state(batch,
+ count * 4 * GENX(SAMPLER_STATE_length),
+ 32, &offset);
- for (unsigned i = 0; i < cso->num_buffers; i++) {
- *addr = iris_batch_reloc(batch, (void *) addr - batch->cmdbuf.map,
- cso->bos[i].bo, cso->bos[i].offset +
- *delta, cso->bos[i].reloc_flags);
- addr = (void *) addr + 16;
- delta = (void *) delta + 16;
+ for (int i = 0; i < count; i++) {
+ // XXX: when we have a correct count, these better be bound
+ if (!ice->state.samplers[stage][i])
+ continue;
+ memcpy(map, ice->state.samplers[stage][i]->sampler_state,
+ 4 * GENX(SAMPLER_STATE_length));
+ map += GENX(SAMPLER_STATE_length);
}
- }
- if (dirty & IRIS_DIRTY_VERTEX_ELEMENTS) {
- struct iris_vertex_element_state *cso = ice->state.cso_vertex_elements;
- iris_batch_emit(batch, cso->vertex_elements, sizeof(uint32_t) *
- (1 + cso->count * GENX(VERTEX_ELEMENT_STATE_length)));
- for (int i = 0; i < cso->count; i++) {
- iris_batch_emit(batch, cso->vf_instancing[i], sizeof(uint32_t) *
- (cso->count * GENX(3DSTATE_VF_INSTANCING_length)));
- }
- for (int i = 0; i < cso->count; i++) {
- /* TODO: vertexid, instanceid support */
- iris_emit_cmd(batch, GENX(3DSTATE_VF_SGVS), sgvs);
+ iris_emit_cmd(batch, GENX(3DSTATE_SAMPLER_STATE_POINTERS_VS), ptr) {
+ ptr._3DCommandSubOpcode = 43 + stage;
+ ptr.PointertoVSSamplerState = offset;
}
}
}
}
- for (int stage = 0; stage <= MESA_SHADER_FRAGMENT; stage++) {
- if (!(dirty & (IRIS_DIRTY_SAMPLER_STATES_VS << stage)))
- continue;
+ // XXX: SOL and so on
- // XXX: get sampler count from shader; don't emit them all...
- const int count = IRIS_MAX_TEXTURE_SAMPLERS;
+ if (dirty & IRIS_DIRTY_CLIP) {
+ struct iris_rasterizer_state *cso = ice->state.cso_rast;
- uint32_t offset;
- uint32_t *map = iris_alloc_state(batch,
- count * 4 * GENX(SAMPLER_STATE_length),
- 32, &offset);
+ uint32_t dynamic_clip[GENX(3DSTATE_CLIP_length)];
+ iris_pack_command(GENX(3DSTATE_CLIP), &dynamic_clip, cl) {
+ //.NonPerspectiveBarycentricEnable = <comes from FS prog> :(
+ //.ForceZeroRTAIndexEnable = <comes from FB layers being 0>
+ // also userclip stuffs...
+ }
+ iris_emit_merge(batch, cso->clip, dynamic_clip, ARRAY_SIZE(cso->clip));
+ }
- for (int i = 0; i < count; i++) {
- // XXX: when we have a correct count, these better be bound
- if (!ice->state.samplers[stage][i])
- continue;
- memcpy(map, ice->state.samplers[stage][i]->sampler_state,
- 4 * GENX(SAMPLER_STATE_length));
- map += GENX(SAMPLER_STATE_length);
+ if (dirty & IRIS_DIRTY_RASTER) {
+ struct iris_rasterizer_state *cso = ice->state.cso_rast;
+ iris_batch_emit(batch, cso->raster, sizeof(cso->raster));
+ iris_batch_emit(batch, cso->sf, sizeof(cso->sf));
+ // XXX: 3DSTATE_WM
+ }
+
+ // XXX: SBE, SBE_SWIZ
+
+ if (dirty & IRIS_DIRTY_PS_BLEND) {
+ struct iris_blend_state *cso = ice->state.cso_blend;
+ iris_batch_emit(batch, cso->ps_blend, sizeof(cso->ps_blend));
+ }
+
+ if (dirty & IRIS_DIRTY_WM_DEPTH_STENCIL) {
+ struct iris_depth_stencil_alpha_state *cso = ice->state.cso_zsa;
+ struct pipe_stencil_ref *p_stencil_refs = &ice->state.stencil_ref;
+
+ uint32_t stencil_refs[GENX(3DSTATE_WM_DEPTH_STENCIL_length)];
+ iris_pack_command(GENX(3DSTATE_WM_DEPTH_STENCIL), &stencil_refs, wmds) {
+ wmds.StencilReferenceValue = p_stencil_refs->ref_value[0];
+ wmds.BackfaceStencilReferenceValue = p_stencil_refs->ref_value[1];
}
+ iris_emit_merge(batch, cso->wmds, stencil_refs, ARRAY_SIZE(cso->wmds));
+ }
- iris_emit_cmd(batch, GENX(3DSTATE_SAMPLER_STATE_POINTERS_VS), ptr) {
- ptr._3DCommandSubOpcode = 43 + stage;
- ptr.PointertoVSSamplerState = offset;
+ if (dirty & IRIS_DIRTY_SCISSOR) {
+ uint32_t scissor_offset =
+ iris_emit_state(batch, ice->state.scissors,
+ sizeof(struct pipe_scissor_state) *
+ ice->state.num_scissors, 32);
+
+ iris_emit_cmd(batch, GENX(3DSTATE_SCISSOR_STATE_POINTERS), ptr) {
+ ptr.ScissorRectPointer = scissor_offset;
}
}
- if (1) {
- iris_emit_cmd(batch, GENX(3DSTATE_VF_TOPOLOGY), topo) {
- topo.PrimitiveTopologyType =
- translate_prim_type(draw->mode, draw->vertices_per_patch);
+ // XXX: 3DSTATE_DEPTH_BUFFER and friends
+
+ if (dirty & IRIS_DIRTY_POLYGON_STIPPLE) {
+ iris_emit_cmd(batch, GENX(3DSTATE_POLY_STIPPLE_PATTERN), poly) {
+ for (int i = 0; i < 32; i++) {
+ poly.PatternRow[i] = ice->state.poly_stipple.stipple[i];
+ }
}
}
+ if (dirty & IRIS_DIRTY_LINE_STIPPLE) {
+ struct iris_rasterizer_state *cso = ice->state.cso_rast;
+ iris_batch_emit(batch, cso->line_stipple, sizeof(cso->line_stipple));
+ }
+
if (1) {
- iris_emit_cmd(batch, GENX(3DSTATE_VF), vf) {
- if (draw->primitive_restart) {
- vf.IndexedDrawCutIndexEnable = true;
- vf.CutIndex = draw->restart_index;
- }
+ iris_emit_cmd(batch, GENX(3DSTATE_VF_TOPOLOGY), topo) {
+ topo.PrimitiveTopologyType =
+ translate_prim_type(draw->mode, draw->vertices_per_patch);
}
}
- // draw->index_size > 0
if (draw->index_size > 0) {
struct iris_resource *res = (struct iris_resource *)draw->index.resource;
}
}
+ if (dirty & IRIS_DIRTY_VERTEX_BUFFERS) {
+ struct iris_vertex_buffer_state *cso = ice->state.cso_vertex_buffers;
+
+ STATIC_ASSERT(GENX(VERTEX_BUFFER_STATE_length) == 4);
+ STATIC_ASSERT((GENX(VERTEX_BUFFER_STATE_BufferStartingAddress_bits) % 32) == 0);
+
+ uint64_t *addr = batch->cmdbuf.map_next + sizeof(uint32_t) *
+ (GENX(VERTEX_BUFFER_STATE_BufferStartingAddress_bits) / 32);
+ uint32_t *delta = cso->vertex_buffers +
+ (1 + GENX(VERTEX_BUFFER_STATE_BufferStartingAddress_bits) / 32);
+
+ iris_batch_emit(batch, cso->vertex_buffers,
+ sizeof(uint32_t) * (1 + 4 * cso->num_buffers));
+
+ for (unsigned i = 0; i < cso->num_buffers; i++) {
+ *addr = iris_batch_reloc(batch, (void *) addr - batch->cmdbuf.map,
+ cso->bos[i].bo, cso->bos[i].offset +
+ *delta, cso->bos[i].reloc_flags);
+ addr = (void *) addr + 16;
+ delta = (void *) delta + 16;
+ }
+ }
+
+ if (dirty & IRIS_DIRTY_VERTEX_ELEMENTS) {
+ struct iris_vertex_element_state *cso = ice->state.cso_vertex_elements;
+ iris_batch_emit(batch, cso->vertex_elements, sizeof(uint32_t) *
+ (1 + cso->count * GENX(VERTEX_ELEMENT_STATE_length)));
+ for (int i = 0; i < cso->count; i++) {
+ iris_batch_emit(batch, cso->vf_instancing[i], sizeof(uint32_t) *
+ (cso->count * GENX(3DSTATE_VF_INSTANCING_length)));
+ }
+ for (int i = 0; i < cso->count; i++) {
+ /* TODO: vertexid, instanceid support */
+ iris_emit_cmd(batch, GENX(3DSTATE_VF_SGVS), sgvs);
+ }
+ }
+
+ if (1) {
+ iris_emit_cmd(batch, GENX(3DSTATE_VF), vf) {
+ if (draw->primitive_restart) {
+ vf.IndexedDrawCutIndexEnable = true;
+ vf.CutIndex = draw->restart_index;
+ }
+ }
+ }
+
+ // XXX: Gen8 - PMA fix
+
assert(!draw->indirect); // XXX: indirect support
iris_emit_cmd(batch, GENX(3DPRIMITIVE), prim) {
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