Merge ktlim@zizzer:/bk/newmem

into  zamp.eecs.umich.edu:/z/ktlim2/clean/tmp/clean2

src/cpu/base_dyn_inst.hh:
    Hand merge.  Line is no longer needed because it's handled in the ISA.

--HG--
extra : convert_revision : 0be4067aa38759a5631c6940f0167d48fde2b680

diff --cc src/arch/alpha/isa/decoder.isa
Simple merge

diff --cc src/cpu/base.cc
Simple merge

diff --cc src/cpu/o3/alpha/cpu_impl.hh
Simple merge

diff --cc src/cpu/o3/commit_impl.hh
Simple merge

diff --cc src/cpu/o3/cpu.cc
index 38e6a0b5beb25ea48cf2ad615cfbb1b834b02ff4,f9e094d751a9486e8971aecd0ada76c049305684..354e3c49054429b4bfcf34246008ece2a4a1b718
--- 1/src/cpu/o3/cpu.cc
--- 2/src/cpu/o3/cpu.cc
+++ b/src/cpu/o3/cpu.cc
@@@ -983,7 -977,26 +983,7 @@@ FullO3CPU<Impl>::takeOverFrom(BaseCPU *
          }
      }
      if (!tickEvent.scheduled())
-         tickEvent.schedule(curTick);
+         tickEvent.schedule(nextCycle());
 -
 -    Port *peer;
 -    Port *icachePort = fetch.getIcachePort();
 -    if (icachePort->getPeer() == NULL) {
 -        peer = oldCPU->getPort("icache_port")->getPeer();
 -        icachePort->setPeer(peer);
 -    } else {
 -        peer = icachePort->getPeer();
 -    }
 -    peer->setPeer(icachePort);
 -
 -    Port *dcachePort = iew.getDcachePort();
 -    if (dcachePort->getPeer() == NULL) {
 -        peer = oldCPU->getPort("dcache_port")->getPeer();
 -        dcachePort->setPeer(peer);
 -    } else {
 -        peer = dcachePort->getPeer();
 -    }
 -    peer->setPeer(dcachePort);
  }
  
  template <class Impl>

diff --cc src/cpu/o3/cpu.hh
Simple merge

diff --cc src/cpu/o3/fetch_impl.hh
Simple merge

diff --cc src/cpu/o3/inst_queue_impl.hh
Simple merge

diff --cc src/cpu/o3/lsq_unit.hh
Simple merge

diff --cc src/cpu/o3/lsq_unit_impl.hh
Simple merge

diff --cc src/mem/bus.cc
Simple merge

diff --cc src/mem/cache/cache_impl.hh
Simple merge

diff --cc src/mem/cache/miss/miss_queue.cc
index 25b8fcbebc21c555c9826238c613e0670341ab65,38c5ffa7127bab50a1455f2bc9d2f749c9757076..24ca9cfa2e517e06c52ad2081a5d7c0ec64612e3
--- 1/src/mem/cache/miss/miss_queue.cc
--- 2/src/mem/cache/miss/miss_queue.cc
+++ b/src/mem/cache/miss/miss_queue.cc
@@@ -596,9 -601,10 +596,10 @@@ MissQueue::handleResponse(PacketPtr &pk
  
          if (mshr->hasTargets()) {
              // Didn't satisfy all the targets, need to resend
 -            Packet::Command cmd = mshr->getTarget()->cmd;
 +            MemCmd cmd = mshr->getTarget()->cmd;
              mshr->pkt->setDest(Packet::Broadcast);
              mshr->pkt->result = Packet::Unknown;
+             mshr->pkt->req = mshr->getTarget()->req;
              mq.markPending(mshr, cmd);
              mshr->order = order++;
              cache->setMasterRequest(Request_MSHR, time);