Added k68 (m68k compatible cpu) test case from verilator

diff --git a/tests/k68_vltor/changes.diff b/tests/k68_vltor/changes.diff
new file mode 100644 (file)
index 0000000..80d5da9
--- /dev/null
+++ b/tests/k68_vltor/changes.diff
@@ -0,0 +1,25 @@
+diff --git a/bench/bench.cpp b/bench/bench.cpp
+index 47a50c4..de27fbb 100755
+--- a/bench/bench.cpp
++++ b/bench/bench.cpp
+@@ -71,6 +71,7 @@ int main(int argc, char **argv, char **env) {
+       main_time++;
+       top->arbclk_i = !top->arbclk_i;
+       if (main_time%5 == 0) top->clk = !top->clk;
++      if (main_time%100000 == 0) cout<<"Partial sum = "<<hex<<top->sum<<"\n";
+     }
+ 
+     cout<<"Final sum = "<<hex<<top->sum<<"\n";
+diff --git a/rtl/k68_clkgen.v b/rtl/k68_clkgen.v
+index c201a97..55b9cad 100755
+--- a/rtl/k68_clkgen.v
++++ b/rtl/k68_clkgen.v
+@@ -57,7 +57,7 @@ module k68_clkgen (/*AUTOARG*/
+    assign    clk4_o = cnt[1];
+    assign    clk_o = ~clk_i;
+    
+-   initial cnt = 0;   // Power up state doesn't matter, but can't be X
++   // initial cnt = 0;        // Power up state doesn't matter, but can't be X
+ 
+    always @(posedge clk_i) begin
+       cnt <= cnt + 1'b1;

diff --git a/tests/k68_vltor/clone.sh b/tests/k68_vltor/clone.sh
new file mode 100644 (file)
index 0000000..54bba52
--- /dev/null
+++ b/tests/k68_vltor/clone.sh
@@ -0,0 +1,6 @@
+#!/bin/bash
+set -ex
+rm -rf verilog-sim-benchmarks
+git clone http://git.veripool.org/git/verilog-sim-benchmarks
+cd verilog-sim-benchmarks
+patch -p1 < ../changes.diff

diff --git a/tests/k68_vltor/run.sh b/tests/k68_vltor/run.sh
new file mode 100644 (file)
index 0000000..de831d3
--- /dev/null
+++ b/tests/k68_vltor/run.sh
@@ -0,0 +1,30 @@
+#!/bin/bash
+
+if (
+       set -ex
+       cd verilog-sim-benchmarks
+       rm -rf obj_dir_* synth
+
+       cd rtl
+       mkdir -p ../synth
+       yosys -o ../synth/k68_soc.v -p 'hierarchy -check -top k68_soc; proc; opt; memory; opt' \
+                       k68_soc.v k68_arb.v k68_cpu.v k68_load.v k68_clkgen.v k68_decode.v k68_execute.v \
+                       k68_fetch.v k68_regbank.v k68_buni.v k68_b2d.v k68_ccc.v k68_d2b.v k68_rox.v \
+                       k68_calc.v k68_dpmem.v k68_sasc.v sasc_brg.v sasc_top.v sasc_fifo4.v
+
+       cd ..
+       VERILATOR_OPT="-Wno-fatal -Ibench --cc bench/k68_soc_test.v --exe bench/bench.cpp -prefix m68 -x-assign 0"
+       verilator -Mdir obj_dir_rtl -Irtl $VERILATOR_OPT; make -C obj_dir_rtl -f m68.mk
+       verilator -Mdir obj_dir_synth -Isynth $VERILATOR_OPT; make -C obj_dir_synth -f m68.mk
+
+       ./obj_dir_rtl/m68 100000 | tee output_rtl.txt
+       ./obj_dir_synth/m68 100000 | tee output_synth.txt
+       diff -u <( grep ' sum ' output_rtl.txt; ) <( grep ' sum ' output_synth.txt; )
+); then
+       echo OK
+       exit 0
+else
+       echo ERROR
+       exit 1
+fi
+