soc/csr_bus: improve CSR paging genericity

diff --git a/litex/soc/integration/soc.py b/litex/soc/integration/soc.py
index 54e852d92d824182cafd79a3e41aa2722868b6d7..82589a72c6322f69998cada1a7eb9cb9d2bdbc41 100755 (executable)
--- a/litex/soc/integration/soc.py
+++ b/litex/soc/integration/soc.py
@@ -428,11 +428,11 @@ class SoCCSRHandler(SoCLocHandler):
     supported_data_width    = [8, 32]
     supported_address_width = [14, 15]
     supported_alignment     = [32, 64]
-    supported_paging        = [0x800, 0x1000]
+    supported_paging        = [0x800*2**i for i in range(3)]
 
     # Creation -------------------------------------------------------------------------------------
     def __init__(self, data_width=32, address_width=14, alignment=32, paging=0x800, reserved_csrs={}):
-        SoCLocHandler.__init__(self, "CSR", n_locs=4*2**address_width//paging) # FIXME
+        SoCLocHandler.__init__(self, "CSR", n_locs=alignment//8*(2**address_width)//paging)
         self.logger = logging.getLogger("SoCCSRHandler")
         self.logger.info("Creating CSR Handler...")
 
@@ -468,10 +468,10 @@ class SoCCSRHandler(SoCLocHandler):
 
         # Check Paging
         if paging not in self.supported_paging:
-            self.logger.error("Unsupported {} {}, supporteds: {:s}".format(
+            self.logger.error("Unsupported {} 0x{}, supporteds: {:s}".format(
                 colorer("Paging", color="red"),
-                colorer(paging),
-                colorer(", ".join(str(x) for x in self.supported_paging))))
+                colorer("{:x}".format(paging)),
+                colorer(", ".join("0x{:x}".format(x) for x in self.supported_paging))))
             raise
 
         # Create CSR Handler

diff --git a/litex/soc/interconnect/csr_bus.py b/litex/soc/interconnect/csr_bus.py
index c07a812e37d2e77582c87f6c26729505f3a4dfdf..0944eef4c814abcb6e539883d86d4d7673c88d77 100644 (file)
--- a/litex/soc/interconnect/csr_bus.py
+++ b/litex/soc/interconnect/csr_bus.py
@@ -78,22 +78,23 @@ class InterconnectShared(Module):
 
 
 class SRAM(Module):
-    def __init__(self, mem_or_size, address, paging=0x800, read_only=None, init=None, bus=None):
+    def __init__(self, mem_or_size, address, read_only=None, init=None, bus=None, paging=0x800):
         if bus is None:
             bus = Interface()
         self.bus = bus
+        aligned_paging = paging//(bus.alignment//8)
         data_width = len(self.bus.dat_w)
         if isinstance(mem_or_size, Memory):
             mem = mem_or_size
         else:
             mem = Memory(data_width, mem_or_size//(data_width//8), init=init)
         mem_size = int(mem.width*mem.depth/8)
-        if mem_size > paging//4:
+        if mem_size > aligned_paging:
             print("WARNING: memory > {} bytes in CSR region requires paged access (mem_size = {} bytes)".format(
                 paging//4, mem_size))
         csrw_per_memw = (mem.width + data_width - 1)//data_width
         word_bits = log2_int(csrw_per_memw)
-        page_bits = log2_int((mem.depth*csrw_per_memw + paging//4 - 1)//(paging//4), False)
+        page_bits = log2_int((mem.depth*csrw_per_memw + aligned_paging - 1)//aligned_paging, False)
         if page_bits:
             self._page = CSRStorage(page_bits, name=mem.name_override + "_page")
         else:
@@ -112,7 +113,7 @@ class SRAM(Module):
         sel = Signal()
         sel_r = Signal()
         self.sync += sel_r.eq(sel)
-        self.comb += sel.eq(self.bus.adr[log2_int(paging//4):] == address)
+        self.comb += sel.eq(self.bus.adr[log2_int(aligned_paging):] == address)
         if bus.alignment == 64:
             self.comb += If(self.bus.adr[0], sel.eq(0))
 
@@ -165,13 +166,13 @@ class CSRBank(csr.GenericBank):
         if bus is None:
             bus = Interface()
         self.bus = bus
-
+        aligned_paging = paging//(bus.alignment//8)
         ###
 
         csr.GenericBank.__init__(self, description, len(self.bus.dat_w))
 
         sel = Signal()
-        self.comb += sel.eq(self.bus.adr[log2_int(paging//4):] == address)
+        self.comb += sel.eq(self.bus.adr[log2_int(aligned_paging):] == address)
         if bus.alignment == 64:
             self.comb += If(self.bus.adr[0], sel.eq(0))