Fix constraints.

2011-06-28  Ramana Radhakrishnan  <ramana.radhakrishnan@linaro.org>

       * config/arm/vfp.md ("*divsf3_vfp"): Replace '+' constraint modifier
       with '=' constraint modifier.
       (*divdf3_vfp): Likewise.
       ("*mulsf3_vfp"): Likewise.
       ("*muldf3_vfp"): Likewise.
       ("*mulsf3negsf_vfp"): Likewise.
       ("*muldf3negdf_vfp"): Likewise.

From-SVN: r175588

diff --git a/gcc/ChangeLog b/gcc/ChangeLog
index 1ce67633953c2a4fc3b39c06ce5e5bc52933b6b2..23997c43a41bbad0e7645a052ff0b9442385f660 100644 (file)
--- a/gcc/ChangeLog
+++ b/gcc/ChangeLog
@@ -1,3 +1,13 @@
+2011-06-28  Ramana Radhakrishnan  <ramana.radhakrishnan@linaro.org>
+
+       * config/arm/vfp.md ("*divsf3_vfp"): Replace '+' constraint modifier
+       with '=' constraint modifier.
+       (*divdf3_vfp): Likewise.
+       ("*mulsf3_vfp"): Likewise.
+       ("*muldf3_vfp"): Likewise.
+       ("*mulsf3negsf_vfp"): Likewise.
+       ("*muldf3negdf_vfp"): Likewise.
+
 2011-06-28  Nick Clifton  <nickc@redhat.com>
 
        * config/mn10300/mn10300.h (LINK_SPEC): Do not use linker

diff --git a/gcc/config/arm/vfp.md b/gcc/config/arm/vfp.md
index 42be2ff3acc40f95db9f47e181d6c67c2e324b73..e2165a8cfe3eff08fe4114eef02d0cbaead71a9f 100644 (file)
--- a/gcc/config/arm/vfp.md
+++ b/gcc/config/arm/vfp.md
@@ -719,7 +719,7 @@
 ;; Division insns
 
 (define_insn "*divsf3_vfp"
-  [(set (match_operand:SF        0 "s_register_operand" "+t")
+  [(set (match_operand:SF        0 "s_register_operand" "=t")
        (div:SF (match_operand:SF 1 "s_register_operand" "t")
                (match_operand:SF 2 "s_register_operand" "t")))]
   "TARGET_32BIT && TARGET_HARD_FLOAT && TARGET_VFP"
@@ -729,7 +729,7 @@
 )
 
 (define_insn "*divdf3_vfp"
-  [(set (match_operand:DF        0 "s_register_operand" "+w")
+  [(set (match_operand:DF        0 "s_register_operand" "=w")
        (div:DF (match_operand:DF 1 "s_register_operand" "w")
                (match_operand:DF 2 "s_register_operand" "w")))]
   "TARGET_32BIT && TARGET_HARD_FLOAT && TARGET_VFP_DOUBLE"
@@ -742,7 +742,7 @@
 ;; Multiplication insns
 
 (define_insn "*mulsf3_vfp"
-  [(set (match_operand:SF         0 "s_register_operand" "+t")
+  [(set (match_operand:SF         0 "s_register_operand" "=t")
        (mult:SF (match_operand:SF 1 "s_register_operand" "t")
                 (match_operand:SF 2 "s_register_operand" "t")))]
   "TARGET_32BIT && TARGET_HARD_FLOAT && TARGET_VFP"
@@ -752,7 +752,7 @@
 )
 
 (define_insn "*muldf3_vfp"
-  [(set (match_operand:DF         0 "s_register_operand" "+w")
+  [(set (match_operand:DF         0 "s_register_operand" "=w")
        (mult:DF (match_operand:DF 1 "s_register_operand" "w")
                 (match_operand:DF 2 "s_register_operand" "w")))]
   "TARGET_32BIT && TARGET_HARD_FLOAT && TARGET_VFP_DOUBLE"
@@ -761,9 +761,8 @@
    (set_attr "type" "fmuld")]
 )
 
-
 (define_insn "*mulsf3negsf_vfp"
-  [(set (match_operand:SF                 0 "s_register_operand" "+t")
+  [(set (match_operand:SF                 0 "s_register_operand" "=t")
        (mult:SF (neg:SF (match_operand:SF 1 "s_register_operand" "t"))
                 (match_operand:SF         2 "s_register_operand" "t")))]
   "TARGET_32BIT && TARGET_HARD_FLOAT && TARGET_VFP"
@@ -773,7 +772,7 @@
 )
 
 (define_insn "*muldf3negdf_vfp"
-  [(set (match_operand:DF                 0 "s_register_operand" "+w")
+  [(set (match_operand:DF                 0 "s_register_operand" "=w")
        (mult:DF (neg:DF (match_operand:DF 1 "s_register_operand" "w"))
                 (match_operand:DF         2 "s_register_operand" "w")))]
   "TARGET_32BIT && TARGET_HARD_FLOAT && TARGET_VFP_DOUBLE"