-# Copyright (c) 2012 ARM Limited
+# Copyright (c) 2012, 2017 ARM Limited
# All rights reserved.
#
# The license below extends only to copyright in the software and shall
Arguments:
machine_type -- String describing the platform to simulate
num_cpus -- integer number of CPUs in the system
+ use_ruby -- True if ruby is used instead of the classic memory system
"""
self.machine_type = machine_type
self.num_cpus = kwargs.get('num_cpus', 1)
self.mem_size = kwargs.get('mem_size', '256MB')
+ self.use_ruby = kwargs.get('use_ruby', False)
def create_system(self):
sc = SysConfig(None, self.mem_size, None)
system = FSConfig.makeArmSystem(self.mem_mode,
self.machine_type, self.num_cpus,
- sc, False)
+ sc, False, ruby=self.use_ruby)
# We typically want the simulator to panic if the kernel
# panics or oopses. This prevents the simulator from running
-# Copyright (c) 2012-2013 ARM Limited
+# Copyright (c) 2012-2013, 2017 ARM Limited
# All rights reserved.
#
# The license below extends only to copyright in the software and shall
# Andreas Hansson
from abc import ABCMeta, abstractmethod
+import optparse
import m5
from m5.objects import *
from m5.proxy import *
m5.util.addToPath('../configs/')
from common import FSConfig
+from common import Options
from common.Caches import *
+from ruby import Ruby
_have_kvm_support = 'BaseKvmCPU' in globals()
def __init__(self, mem_mode='timing', mem_class=SimpleMemory,
cpu_class=TimingSimpleCPU, num_cpus=1, num_threads=1,
- checker=False,
- mem_size=None):
+ checker=False, mem_size=None, use_ruby=False):
"""Initialize a simple base system.
Keyword Arguments:
num_cpus -- Number of CPUs to instantiate
checker -- Set to True to add checker CPUs
mem_size -- Override the default memory size
+ use_ruby -- Set to True to use ruby memory
"""
self.mem_mode = mem_mode
self.mem_class = mem_class
self.num_cpus = num_cpus
self.num_threads = num_threads
self.checker = checker
+ self.use_ruby = use_ruby
def create_cpus(self, cpu_clk_domain):
"""Return a list of CPU objects to add to a system."""
any([isinstance(c, BaseKvmCPU) for c in system.cpu]):
self.init_kvm(system)
- sha_bus = self.create_caches_shared(system)
+ if self.use_ruby:
+ # Add the ruby specific and protocol specific options
+ parser = optparse.OptionParser()
+ Options.addCommonOptions(parser)
+ Ruby.define_options(parser)
+ (options, args) = parser.parse_args()
+
+ # Set the default cache size and associativity to be very
+ # small to encourage races between requests and writebacks.
+ options.l1d_size="32kB"
+ options.l1i_size="32kB"
+ options.l2_size="4MB"
+ options.l1d_assoc=4
+ options.l1i_assoc=2
+ options.l2_assoc=8
+ options.num_cpus = self.num_cpus
+ options.num_dirs = 2
+
+ Ruby.create_system(options, True, system, system.iobus,
+ system._dma_ports)
+
+ # Create a seperate clock domain for Ruby
+ system.ruby.clk_domain = SrcClockDomain(
+ clock = options.ruby_clock,
+ voltage_domain = system.voltage_domain)
+ for i, cpu in enumerate(system.cpu):
+ if not cpu.switched_out:
+ cpu.createInterruptController()
+ cpu.connectCachedPorts(system.ruby._cpu_ports[i])
+ else:
+ sha_bus = self.create_caches_shared(system)
+ for cpu in system.cpu:
+ self.init_cpu(system, cpu, sha_bus)
- for cpu in system.cpu:
- self.init_cpu(system, cpu, sha_bus)
def create_clk_src(self,system):
# Create system clock domain. This provides clock value to every
membus = SystemXBar(),
mem_mode = self.mem_mode,
multi_thread = (self.num_threads > 1))
- system.system_port = system.membus.slave
+ if not self.use_ruby:
+ system.system_port = system.membus.slave
system.physmem.port = system.membus.master
self.init_system(system)
return system
def init_system(self, system):
BaseSystem.init_system(self, system)
- # create the memory controllers and connect them, stick with
- # the physmem name to avoid bumping all the reference stats
- system.physmem = [self.mem_class(range = r)
- for r in system.mem_ranges]
- for i in xrange(len(system.physmem)):
- system.physmem[i].port = system.membus.master
-
- # create the iocache, which by default runs at the system clock
- system.iocache = IOCache(addr_ranges=system.mem_ranges)
- system.iocache.cpu_side = system.iobus.master
- system.iocache.mem_side = system.membus.slave
+ if self.use_ruby:
+ # Connect the ruby io port to the PIO bus,
+ # assuming that there is just one such port.
+ system.iobus.master = system.ruby._io_port.slave
+ else:
+ # create the memory controllers and connect them, stick with
+ # the physmem name to avoid bumping all the reference stats
+ system.physmem = [self.mem_class(range = r)
+ for r in system.mem_ranges]
+ for i in xrange(len(system.physmem)):
+ system.physmem[i].port = system.membus.master
+
+ # create the iocache, which by default runs at the system clock
+ system.iocache = IOCache(addr_ranges=system.mem_ranges)
+ system.iocache.cpu_side = system.iobus.master
+ system.iocache.mem_side = system.membus.slave
def create_root(self):
system = self.create_system()
--- /dev/null
+# Copyright (c) 2017 ARM Limited
+# All rights reserved.
+#
+# The license below extends only to copyright in the software and shall
+# not be construed as granting a license to any other intellectual
+# property including but not limited to intellectual property relating
+# to a hardware implementation of the functionality of the software
+# licensed hereunder. You may use the software subject to the license
+# terms below provided that you ensure that this notice is replicated
+# unmodified and in its entirety in all distributions of the software,
+# modified or unmodified, in source code or in binary form.
+#
+# Redistribution and use in source and binary forms, with or without
+# modification, are permitted provided that the following conditions are
+# met: redistributions of source code must retain the above copyright
+# notice, this list of conditions and the following disclaimer;
+# redistributions in binary form must reproduce the above copyright
+# notice, this list of conditions and the following disclaimer in the
+# documentation and/or other materials provided with the distribution;
+# neither the name of the copyright holders nor the names of its
+# contributors may be used to endorse or promote products derived from
+# this software without specific prior written permission.
+#
+# THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
+# "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
+# LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
+# A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT
+# OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,
+# SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
+# LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
+# DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
+# THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
+# (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
+# OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+#
+# Authors: Andreas Sandberg
+
+from m5.objects import *
+from arm_generic import *
+
+root = LinuxArmFSSystem(mem_mode='timing',
+ mem_class=DDR3_1600_8x8,
+ cpu_class=TimingSimpleCPU,
+ num_cpus=2,
+ use_ruby=True).create_root()
+
--- /dev/null
+# Copyright (c) 2017 ARM Limited
+# All rights reserved.
+#
+# The license below extends only to copyright in the software and shall
+# not be construed as granting a license to any other intellectual
+# property including but not limited to intellectual property relating
+# to a hardware implementation of the functionality of the software
+# licensed hereunder. You may use the software subject to the license
+# terms below provided that you ensure that this notice is replicated
+# unmodified and in its entirety in all distributions of the software,
+# modified or unmodified, in source code or in binary form.
+#
+# Redistribution and use in source and binary forms, with or without
+# modification, are permitted provided that the following conditions are
+# met: redistributions of source code must retain the above copyright
+# notice, this list of conditions and the following disclaimer;
+# redistributions in binary form must reproduce the above copyright
+# notice, this list of conditions and the following disclaimer in the
+# documentation and/or other materials provided with the distribution;
+# neither the name of the copyright holders nor the names of its
+# contributors may be used to endorse or promote products derived from
+# this software without specific prior written permission.
+#
+# THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
+# "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
+# LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
+# A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT
+# OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,
+# SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
+# LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
+# DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
+# THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
+# (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
+# OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+#
+# Authors: Andreas Sandberg
+
+from m5.objects import *
+from arm_generic import *
+
+root = LinuxArmFSSystemUniprocessor(mem_mode='timing',
+ mem_class=DDR3_1600_8x8,
+ cpu_class=TimingSimpleCPU,
+ use_ruby=True).create_root()
+
--- /dev/null
+# Copyright (c) 2017 ARM Limited
+# All rights reserved.
+#
+# The license below extends only to copyright in the software and shall
+# not be construed as granting a license to any other intellectual
+# property including but not limited to intellectual property relating
+# to a hardware implementation of the functionality of the software
+# licensed hereunder. You may use the software subject to the license
+# terms below provided that you ensure that this notice is replicated
+# unmodified and in its entirety in all distributions of the software,
+# modified or unmodified, in source code or in binary form.
+#
+# Redistribution and use in source and binary forms, with or without
+# modification, are permitted provided that the following conditions are
+# met: redistributions of source code must retain the above copyright
+# notice, this list of conditions and the following disclaimer;
+# redistributions in binary form must reproduce the above copyright
+# notice, this list of conditions and the following disclaimer in the
+# documentation and/or other materials provided with the distribution;
+# neither the name of the copyright holders nor the names of its
+# contributors may be used to endorse or promote products derived from
+# this software without specific prior written permission.
+#
+# THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
+# "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
+# LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
+# A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT
+# OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,
+# SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
+# LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
+# DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
+# THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
+# (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
+# OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+#
+# Authors: Andreas Sandberg
+
+from m5.objects import *
+from arm_generic import *
+
+root = LinuxArmFSSystem(machine_type='VExpress_EMM64',
+ mem_mode='timing',
+ mem_class=DDR3_1600_8x8,
+ cpu_class=TimingSimpleCPU,
+ num_cpus=2,
+ use_ruby=True).create_root()
+
--- /dev/null
+# Copyright (c) 2017 ARM Limited
+# All rights reserved.
+#
+# The license below extends only to copyright in the software and shall
+# not be construed as granting a license to any other intellectual
+# property including but not limited to intellectual property relating
+# to a hardware implementation of the functionality of the software
+# licensed hereunder. You may use the software subject to the license
+# terms below provided that you ensure that this notice is replicated
+# unmodified and in its entirety in all distributions of the software,
+# modified or unmodified, in source code or in binary form.
+#
+# Redistribution and use in source and binary forms, with or without
+# modification, are permitted provided that the following conditions are
+# met: redistributions of source code must retain the above copyright
+# notice, this list of conditions and the following disclaimer;
+# redistributions in binary form must reproduce the above copyright
+# notice, this list of conditions and the following disclaimer in the
+# documentation and/or other materials provided with the distribution;
+# neither the name of the copyright holders nor the names of its
+# contributors may be used to endorse or promote products derived from
+# this software without specific prior written permission.
+#
+# THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
+# "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
+# LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
+# A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT
+# OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,
+# SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
+# LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
+# DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
+# THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
+# (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
+# OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+#
+# Authors: Andreas Sandberg
+
+from m5.objects import *
+from arm_generic import *
+
+root = LinuxArmFSSystemUniprocessor(machine_type='VExpress_EMM64',
+ mem_mode='timing',
+ mem_class=DDR3_1600_8x8,
+ cpu_class=TimingSimpleCPU,
+ use_ruby=True).create_root()
+
--- /dev/null
+
+---------- Begin Simulation Statistics ----------
+sim_seconds 2.894518
+sim_ticks 2894518015000
+final_tick 2894518015000
+sim_freq 1000000000000
+host_inst_rate 160490
+host_op_rate 193630
+host_tick_rate 3969302938
+host_mem_usage 829632
+host_seconds 729.23
+sim_insts 117033526
+sim_ops 141199810
+system.voltage_domain.voltage 1
+system.clk_domain.clock 1000
+system.mem_ctrls0.pwrStateResidencyTicks::UNDEFINED 2894518015000
+system.mem_ctrls0.bytes_read::ruby.dir_cntrl0 6066368
+system.mem_ctrls0.bytes_read::total 6066368
+system.mem_ctrls0.bytes_written::ruby.dir_cntrl0 4470144
+system.mem_ctrls0.bytes_written::total 4470144
+system.mem_ctrls0.num_reads::ruby.dir_cntrl0 94787
+system.mem_ctrls0.num_reads::total 94787
+system.mem_ctrls0.num_writes::ruby.dir_cntrl0 69846
+system.mem_ctrls0.num_writes::total 69846
+system.mem_ctrls0.bw_read::ruby.dir_cntrl0 2095813
+system.mem_ctrls0.bw_read::total 2095813
+system.mem_ctrls0.bw_write::ruby.dir_cntrl0 1544348
+system.mem_ctrls0.bw_write::total 1544348
+system.mem_ctrls0.bw_total::ruby.dir_cntrl0 3640161
+system.mem_ctrls0.bw_total::total 3640161
+system.mem_ctrls0.readReqs 94787
+system.mem_ctrls0.writeReqs 69846
+system.mem_ctrls0.readBursts 94787
+system.mem_ctrls0.writeBursts 69846
+system.mem_ctrls0.bytesReadDRAM 6052864
+system.mem_ctrls0.bytesReadWrQ 13504
+system.mem_ctrls0.bytesWritten 4468608
+system.mem_ctrls0.bytesReadSys 6066368
+system.mem_ctrls0.bytesWrittenSys 4470144
+system.mem_ctrls0.servicedByWrQ 211
+system.mem_ctrls0.mergedWrBursts 0
+system.mem_ctrls0.neitherReadNorWriteReqs 0
+system.mem_ctrls0.perBankRdBursts::0 6950
+system.mem_ctrls0.perBankRdBursts::1 6637
+system.mem_ctrls0.perBankRdBursts::2 5437
+system.mem_ctrls0.perBankRdBursts::3 6196
+system.mem_ctrls0.perBankRdBursts::4 5957
+system.mem_ctrls0.perBankRdBursts::5 5597
+system.mem_ctrls0.perBankRdBursts::6 5359
+system.mem_ctrls0.perBankRdBursts::7 5164
+system.mem_ctrls0.perBankRdBursts::8 5289
+system.mem_ctrls0.perBankRdBursts::9 5131
+system.mem_ctrls0.perBankRdBursts::10 6244
+system.mem_ctrls0.perBankRdBursts::11 6522
+system.mem_ctrls0.perBankRdBursts::12 5710
+system.mem_ctrls0.perBankRdBursts::13 6158
+system.mem_ctrls0.perBankRdBursts::14 6261
+system.mem_ctrls0.perBankRdBursts::15 5964
+system.mem_ctrls0.perBankWrBursts::0 4983
+system.mem_ctrls0.perBankWrBursts::1 4822
+system.mem_ctrls0.perBankWrBursts::2 3964
+system.mem_ctrls0.perBankWrBursts::3 4511
+system.mem_ctrls0.perBankWrBursts::4 4495
+system.mem_ctrls0.perBankWrBursts::5 4284
+system.mem_ctrls0.perBankWrBursts::6 3997
+system.mem_ctrls0.perBankWrBursts::7 3931
+system.mem_ctrls0.perBankWrBursts::8 4159
+system.mem_ctrls0.perBankWrBursts::9 4052
+system.mem_ctrls0.perBankWrBursts::10 4645
+system.mem_ctrls0.perBankWrBursts::11 4640
+system.mem_ctrls0.perBankWrBursts::12 4126
+system.mem_ctrls0.perBankWrBursts::13 4592
+system.mem_ctrls0.perBankWrBursts::14 4476
+system.mem_ctrls0.perBankWrBursts::15 4145
+system.mem_ctrls0.numRdRetry 0
+system.mem_ctrls0.numWrRetry 0
+system.mem_ctrls0.totGap 2894517214500
+system.mem_ctrls0.readPktSize::0 0
+system.mem_ctrls0.readPktSize::1 0
+system.mem_ctrls0.readPktSize::2 0
+system.mem_ctrls0.readPktSize::3 0
+system.mem_ctrls0.readPktSize::4 0
+system.mem_ctrls0.readPktSize::5 0
+system.mem_ctrls0.readPktSize::6 94787
+system.mem_ctrls0.writePktSize::0 0
+system.mem_ctrls0.writePktSize::1 0
+system.mem_ctrls0.writePktSize::2 0
+system.mem_ctrls0.writePktSize::3 0
+system.mem_ctrls0.writePktSize::4 0
+system.mem_ctrls0.writePktSize::5 0
+system.mem_ctrls0.writePktSize::6 69846
+system.mem_ctrls0.rdQLenPdf::0 94478
+system.mem_ctrls0.rdQLenPdf::1 98
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+system.mem_ctrls0.rdQLenPdf::17 0
+system.mem_ctrls0.rdQLenPdf::18 0
+system.mem_ctrls0.rdQLenPdf::19 0
+system.mem_ctrls0.rdQLenPdf::20 0
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+system.mem_ctrls0.rdQLenPdf::31 0
+system.mem_ctrls0.wrQLenPdf::0 1
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+system.mem_ctrls0.wrQLenPdf::18 3904
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+system.mem_ctrls0.wrQLenPdf::24 3850
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+system.mem_ctrls0.bytesPerActivate::samples 52634
+system.mem_ctrls0.bytesPerActivate::mean 199.897557
+system.mem_ctrls0.bytesPerActivate::gmean 121.831244
+system.mem_ctrls0.bytesPerActivate::stdev 260.506759
+system.mem_ctrls0.bytesPerActivate::0-127 28874 54.86% 54.86%
+system.mem_ctrls0.bytesPerActivate::128-255 12469 23.69% 78.55%
+system.mem_ctrls0.bytesPerActivate::256-383 4077 7.75% 86.29%
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+system.ruby.L1Cache_Controller.MM.L1_Replacement | 389692 81.31% 81.31% | 89579 18.69% 100.00%
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+system.ruby.L1Cache_Controller.MM.Fwd_GETX | 19455 59.75% 59.75% | 13106 40.25% 100.00%
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+system.ruby.L1Cache_Controller.MM.Fwd_GETS | 44877 55.89% 55.89% | 35420 44.11% 100.00%
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+system.ruby.L1Cache_Controller.MM.Fwd_DMA | 212 95.50% 95.50% | 10 4.50% 100.00%
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+system.ruby.L1Cache_Controller.MM_W.Load | 45128 89.53% 89.53% | 5280 10.47% 100.00%
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+system.ruby.L1Cache_Controller.MM_W.Store | 2629131 85.39% 85.39% | 449719 14.61% 100.00%
+system.ruby.L1Cache_Controller.MM_W.Store::total 3078850
+system.ruby.L1Cache_Controller.MM_W.Fwd_GETX | 275 70.33% 70.33% | 116 29.67% 100.00%
+system.ruby.L1Cache_Controller.MM_W.Fwd_GETX::total 391
+system.ruby.L1Cache_Controller.MM_W.Fwd_GETS | 241 27.64% 27.64% | 631 72.36% 100.00%
+system.ruby.L1Cache_Controller.MM_W.Fwd_GETS::total 872
+system.ruby.L1Cache_Controller.MM_W.Use_Timeout | 374571 80.10% 80.10% | 93086 19.90% 100.00%
+system.ruby.L1Cache_Controller.MM_W.Use_Timeout::total 467657
+system.ruby.L1Cache_Controller.IM.Ack | 14493 42.21% 42.21% | 19839 57.79% 100.00%
+system.ruby.L1Cache_Controller.IM.Ack::total 34332
+system.ruby.L1Cache_Controller.IM.Exclusive_Data | 266268 80.42% 80.42% | 64840 19.58% 100.00%
+system.ruby.L1Cache_Controller.IM.Exclusive_Data::total 331108
+system.ruby.L1Cache_Controller.SM.Inv | 1 50.00% 50.00% | 1 50.00% 100.00%
+system.ruby.L1Cache_Controller.SM.Inv::total 2
+system.ruby.L1Cache_Controller.SM.Ack | 4819 53.23% 53.23% | 4234 46.77% 100.00%
+system.ruby.L1Cache_Controller.SM.Ack::total 9053
+system.ruby.L1Cache_Controller.SM.Exclusive_Data | 7919 57.57% 57.57% | 5836 42.43% 100.00%
+system.ruby.L1Cache_Controller.SM.Exclusive_Data::total 13755
+system.ruby.L1Cache_Controller.OM.Own_GETX | 103 39.16% 39.16% | 160 60.84% 100.00%
+system.ruby.L1Cache_Controller.OM.Own_GETX::total 263
+system.ruby.L1Cache_Controller.OM.Fwd_GETX | 1 7.69% 7.69% | 12 92.31% 100.00%
+system.ruby.L1Cache_Controller.OM.Fwd_GETX::total 13
+system.ruby.L1Cache_Controller.OM.Ack | 432 52.88% 52.88% | 385 47.12% 100.00%
+system.ruby.L1Cache_Controller.OM.Ack::total 817
+system.ruby.L1Cache_Controller.OM.All_acks | 274290 79.48% 79.48% | 70836 20.52% 100.00%
+system.ruby.L1Cache_Controller.OM.All_acks::total 345126
+system.ruby.L1Cache_Controller.IS.Data | 1376641 68.96% 68.96% | 619533 31.04% 100.00%
+system.ruby.L1Cache_Controller.IS.Data::total 1996174
+system.ruby.L1Cache_Controller.IS.Exclusive_Data | 295432 72.19% 72.19% | 113786 27.81% 100.00%
+system.ruby.L1Cache_Controller.IS.Exclusive_Data::total 409218
+system.ruby.L1Cache_Controller.SI.Load | 135958 74.45% 74.45% | 46670 25.55% 100.00%
+system.ruby.L1Cache_Controller.SI.Load::total 182628
+system.ruby.L1Cache_Controller.SI.Ifetch | 146215 73.13% 73.13% | 53735 26.87% 100.00%
+system.ruby.L1Cache_Controller.SI.Ifetch::total 199950
+system.ruby.L1Cache_Controller.SI.Store | 18 100.00% 100.00% | 0 0.00% 100.00%
+system.ruby.L1Cache_Controller.SI.Store::total 18
+system.ruby.L1Cache_Controller.SI.Writeback_Ack | 1344380 68.92% 68.92% | 606151 31.08% 100.00%
+system.ruby.L1Cache_Controller.SI.Writeback_Ack::total 1950531
+system.ruby.L1Cache_Controller.SI.Writeback_Ack_Data | 23417 78.06% 78.06% | 6580 21.94% 100.00%
+system.ruby.L1Cache_Controller.SI.Writeback_Ack_Data::total 29997
+system.ruby.L1Cache_Controller.OI.Load | 184 12.23% 12.23% | 1320 87.77% 100.00%
+system.ruby.L1Cache_Controller.OI.Load::total 1504
+system.ruby.L1Cache_Controller.OI.Ifetch | 47 40.87% 40.87% | 68 59.13% 100.00%
+system.ruby.L1Cache_Controller.OI.Ifetch::total 115
+system.ruby.L1Cache_Controller.OI.Fwd_GETS | 8 44.44% 44.44% | 10 55.56% 100.00%
+system.ruby.L1Cache_Controller.OI.Fwd_GETS::total 18
+system.ruby.L1Cache_Controller.OI.Writeback_Ack_Data | 2753 40.21% 40.21% | 4093 59.79% 100.00%
+system.ruby.L1Cache_Controller.OI.Writeback_Ack_Data::total 6846
+system.ruby.L1Cache_Controller.OI.Writeback_Nack | 1 50.00% 50.00% | 1 50.00% 100.00%
+system.ruby.L1Cache_Controller.OI.Writeback_Nack::total 2
+system.ruby.L1Cache_Controller.MI.Load | 466 67.24% 67.24% | 227 32.76% 100.00%
+system.ruby.L1Cache_Controller.MI.Load::total 693
+system.ruby.L1Cache_Controller.MI.Ifetch | 586 28.78% 28.78% | 1450 71.22% 100.00%
+system.ruby.L1Cache_Controller.MI.Ifetch::total 2036
+system.ruby.L1Cache_Controller.MI.Fwd_GETS | 13 41.94% 41.94% | 18 58.06% 100.00%
+system.ruby.L1Cache_Controller.MI.Fwd_GETS::total 31
+system.ruby.L1Cache_Controller.MI.Writeback_Ack_Data | 497581 79.87% 79.87% | 125410 20.13% 100.00%
+system.ruby.L1Cache_Controller.MI.Writeback_Ack_Data::total 622991
+system.ruby.L2Cache_Controller.L1_GETS 2407512 0.00% 0.00%
+system.ruby.L2Cache_Controller.L1_GETX 345217 0.00% 0.00%
+system.ruby.L2Cache_Controller.L1_PUTO 6889 0.00% 0.00%
+system.ruby.L2Cache_Controller.L1_PUTX 623101 0.00% 0.00%
+system.ruby.L2Cache_Controller.L1_PUTS_only 1475996 0.00% 0.00%
+system.ruby.L2Cache_Controller.L1_PUTS 505327 0.00% 0.00%
+system.ruby.L2Cache_Controller.Fwd_GETX 4433 0.00% 0.00%
+system.ruby.L2Cache_Controller.Fwd_DMA 222 0.00% 0.00%
+system.ruby.L2Cache_Controller.Inv 13 0.00% 0.00%
+system.ruby.L2Cache_Controller.All_Acks 154843 0.00% 0.00%
+system.ruby.L2Cache_Controller.Data 188666 0.00% 0.00%
+system.ruby.L2Cache_Controller.Data_Exclusive 28 0.00% 0.00%
+system.ruby.L2Cache_Controller.L1_WBCLEANDATA 29997 0.00% 0.00%
+system.ruby.L2Cache_Controller.L1_WBDIRTYDATA 629837 0.00% 0.00%
+system.ruby.L2Cache_Controller.Writeback_Ack 103200 0.00% 0.00%
+system.ruby.L2Cache_Controller.Unblock 3946704 0.00% 0.00%
+system.ruby.L2Cache_Controller.Exclusive_Unblock 754344 0.00% 0.00%
+system.ruby.L2Cache_Controller.DmaAck 222 0.00% 0.00%
+system.ruby.L2Cache_Controller.L2_Replacement 112649 0.00% 0.00%
+system.ruby.L2Cache_Controller.NP.L1_GETS 33820 0.00% 0.00%
+system.ruby.L2Cache_Controller.NP.L1_GETX 148628 0.00% 0.00%
+system.ruby.L2Cache_Controller.I.L1_GETS 3 0.00% 0.00%
+system.ruby.L2Cache_Controller.ILS.L1_GETS 355 0.00% 0.00%
+system.ruby.L2Cache_Controller.ILS.L1_GETX 3845 0.00% 0.00%
+system.ruby.L2Cache_Controller.ILS.L1_PUTS_only 29644 0.00% 0.00%
+system.ruby.L2Cache_Controller.ILS.L1_PUTS 353 0.00% 0.00%
+system.ruby.L2Cache_Controller.ILX.L1_GETS 96664 0.00% 0.00%
+system.ruby.L2Cache_Controller.ILX.L1_GETX 34188 0.00% 0.00%
+system.ruby.L2Cache_Controller.ILX.L1_PUTX 622991 0.00% 0.00%
+system.ruby.L2Cache_Controller.ILX.Fwd_GETX 28 0.00% 0.00%
+system.ruby.L2Cache_Controller.ILX.Fwd_DMA 222 0.00% 0.00%
+system.ruby.L2Cache_Controller.ILOX.L1_GETS 11208 0.00% 0.00%
+system.ruby.L2Cache_Controller.ILOX.L1_GETX 167 0.00% 0.00%
+system.ruby.L2Cache_Controller.ILOX.L1_PUTO 3596 0.00% 0.00%
+system.ruby.L2Cache_Controller.ILOX.L1_PUTX 2 0.00% 0.00%
+system.ruby.L2Cache_Controller.ILOSX.L1_GETX 9293 0.00% 0.00%
+system.ruby.L2Cache_Controller.ILOSX.L1_PUTO 3221 0.00% 0.00%
+system.ruby.L2Cache_Controller.ILOSX.L1_PUTX 29 0.00% 0.00%
+system.ruby.L2Cache_Controller.ILOSX.L1_PUTS_only 15016 0.00% 0.00%
+system.ruby.L2Cache_Controller.S.L1_GETS 1429468 0.00% 0.00%
+system.ruby.L2Cache_Controller.S.L1_GETX 2043 0.00% 0.00%
+system.ruby.L2Cache_Controller.S.Inv 13 0.00% 0.00%
+system.ruby.L2Cache_Controller.S.L2_Replacement 9429 0.00% 0.00%
+system.ruby.L2Cache_Controller.OLSX.L1_GETS 24410 0.00% 0.00%
+system.ruby.L2Cache_Controller.OLSX.L1_GETX 610 0.00% 0.00%
+system.ruby.L2Cache_Controller.OLSX.L1_PUTS_only 2575 0.00% 0.00%
+system.ruby.L2Cache_Controller.OLSX.L1_PUTS 24172 0.00% 0.00%
+system.ruby.L2Cache_Controller.SLS.L1_GETS 480543 0.00% 0.00%
+system.ruby.L2Cache_Controller.SLS.L1_GETX 327 0.00% 0.00%
+system.ruby.L2Cache_Controller.SLS.L1_PUTS_only 1428342 0.00% 0.00%
+system.ruby.L2Cache_Controller.SLS.L1_PUTS 480427 0.00% 0.00%
+system.ruby.L2Cache_Controller.SLS.L2_Replacement 20 0.00% 0.00%
+system.ruby.L2Cache_Controller.M.L1_GETS 328921 0.00% 0.00%
+system.ruby.L2Cache_Controller.M.L1_GETX 146025 0.00% 0.00%
+system.ruby.L2Cache_Controller.M.Fwd_GETX 4405 0.00% 0.00%
+system.ruby.L2Cache_Controller.M.L2_Replacement 103200 0.00% 0.00%
+system.ruby.L2Cache_Controller.IFGX.Data_Exclusive 28 0.00% 0.00%
+system.ruby.L2Cache_Controller.ILOXW.L1_GETS 2 0.00% 0.00%
+system.ruby.L2Cache_Controller.ILOXW.L1_PUTO 28 0.00% 0.00%
+system.ruby.L2Cache_Controller.ILOXW.L1_PUTX 10 0.00% 0.00%
+system.ruby.L2Cache_Controller.ILOXW.L1_WBDIRTYDATA 3596 0.00% 0.00%
+system.ruby.L2Cache_Controller.ILOXW.Unblock 15016 0.00% 0.00%
+system.ruby.L2Cache_Controller.ILOSXW.L1_PUTS_only 30 0.00% 0.00%
+system.ruby.L2Cache_Controller.ILOSXW.L1_WBDIRTYDATA 3250 0.00% 0.00%
+system.ruby.L2Cache_Controller.SLSW.L1_GETS 378 0.00% 0.00%
+system.ruby.L2Cache_Controller.SLSW.L1_PUTS 368 0.00% 0.00%
+system.ruby.L2Cache_Controller.SLSW.Unblock 480427 0.00% 0.00%
+system.ruby.L2Cache_Controller.ILSW.L1_WBCLEANDATA 353 0.00% 0.00%
+system.ruby.L2Cache_Controller.IW.L1_GETS 1 0.00% 0.00%
+system.ruby.L2Cache_Controller.IW.L1_WBCLEANDATA 29644 0.00% 0.00%
+system.ruby.L2Cache_Controller.SW.L1_GETS 658 0.00% 0.00%
+system.ruby.L2Cache_Controller.SW.Unblock 1428341 0.00% 0.00%
+system.ruby.L2Cache_Controller.OXW.L1_GETS 21 0.00% 0.00%
+system.ruby.L2Cache_Controller.OXW.Unblock 2575 0.00% 0.00%
+system.ruby.L2Cache_Controller.OLSXW.L1_PUTS 2 0.00% 0.00%
+system.ruby.L2Cache_Controller.OLSXW.Unblock 24172 0.00% 0.00%
+system.ruby.L2Cache_Controller.ILXW.L1_GETS 60 0.00% 0.00%
+system.ruby.L2Cache_Controller.ILXW.L1_GETX 5 0.00% 0.00%
+system.ruby.L2Cache_Controller.ILXW.L1_WBDIRTYDATA 622991 0.00% 0.00%
+system.ruby.L2Cache_Controller.IFLS.Unblock 355 0.00% 0.00%
+system.ruby.L2Cache_Controller.IFLOX.L1_PUTO 35 0.00% 0.00%
+system.ruby.L2Cache_Controller.IFLOX.L1_PUTX 8 0.00% 0.00%
+system.ruby.L2Cache_Controller.IFLOX.Unblock 11208 0.00% 0.00%
+system.ruby.L2Cache_Controller.IFLOX.Exclusive_Unblock 610 0.00% 0.00%
+system.ruby.L2Cache_Controller.IFLOXX.L1_GETS 117 0.00% 0.00%
+system.ruby.L2Cache_Controller.IFLOXX.L1_GETX 41 0.00% 0.00%
+system.ruby.L2Cache_Controller.IFLOXX.L1_PUTO 9 0.00% 0.00%
+system.ruby.L2Cache_Controller.IFLOXX.L1_PUTX 61 0.00% 0.00%
+system.ruby.L2Cache_Controller.IFLOXX.Unblock 16367 0.00% 0.00%
+system.ruby.L2Cache_Controller.IFLOXX.Exclusive_Unblock 114652 0.00% 0.00%
+system.ruby.L2Cache_Controller.IFLXO.L1_GETS 53 0.00% 0.00%
+system.ruby.L2Cache_Controller.IFLXO.L1_GETX 45 0.00% 0.00%
+system.ruby.L2Cache_Controller.IFLXO.Exclusive_Unblock 9293 0.00% 0.00%
+system.ruby.L2Cache_Controller.IGS.L1_GETS 335 0.00% 0.00%
+system.ruby.L2Cache_Controller.IGS.Data 33823 0.00% 0.00%
+system.ruby.L2Cache_Controller.IGS.Unblock 33823 0.00% 0.00%
+system.ruby.L2Cache_Controller.IGM.Data 150671 0.00% 0.00%
+system.ruby.L2Cache_Controller.IGMLS.Data 4172 0.00% 0.00%
+system.ruby.L2Cache_Controller.IGMO.All_Acks 154843 0.00% 0.00%
+system.ruby.L2Cache_Controller.IGMO.Exclusive_Unblock 154843 0.00% 0.00%
+system.ruby.L2Cache_Controller.MM.Exclusive_Unblock 146025 0.00% 0.00%
+system.ruby.L2Cache_Controller.SS.L1_GETS 449 0.00% 0.00%
+system.ruby.L2Cache_Controller.SS.L1_PUTS 3 0.00% 0.00%
+system.ruby.L2Cache_Controller.SS.Unblock 1429467 0.00% 0.00%
+system.ruby.L2Cache_Controller.OO.L1_GETS 46 0.00% 0.00%
+system.ruby.L2Cache_Controller.OO.Exclusive_Unblock 328921 0.00% 0.00%
+system.ruby.L2Cache_Controller.OLSXS.L1_PUTS_only 17 0.00% 0.00%
+system.ruby.L2Cache_Controller.OLSXS.Unblock 24410 0.00% 0.00%
+system.ruby.L2Cache_Controller.SLSS.L1_PUTS_only 372 0.00% 0.00%
+system.ruby.L2Cache_Controller.SLSS.L1_PUTS 2 0.00% 0.00%
+system.ruby.L2Cache_Controller.SLSS.Unblock 480543 0.00% 0.00%
+system.ruby.L2Cache_Controller.MI.Writeback_Ack 103200 0.00% 0.00%
+system.ruby.L2Cache_Controller.ILXD.DmaAck 222 0.00% 0.00%
+
+---------- End Simulation Statistics ----------
--- /dev/null
+
+---------- Begin Simulation Statistics ----------
+sim_seconds 2.877637
+sim_ticks 2877636763500
+final_tick 2877636763500
+sim_freq 1000000000000
+host_inst_rate 167948
+host_op_rate 202496
+host_tick_rate 4296410981
+host_mem_usage 819776
+host_seconds 669.78
+sim_insts 112487545
+sim_ops 135626969
+system.voltage_domain.voltage 1
+system.clk_domain.clock 1000
+system.mem_ctrls0.pwrStateResidencyTicks::UNDEFINED 2877636763500
+system.mem_ctrls0.bytes_read::ruby.dir_cntrl0 5371712
+system.mem_ctrls0.bytes_read::total 5371712
+system.mem_ctrls0.bytes_written::ruby.dir_cntrl0 3874880
+system.mem_ctrls0.bytes_written::total 3874880
+system.mem_ctrls0.num_reads::ruby.dir_cntrl0 83933
+system.mem_ctrls0.num_reads::total 83933
+system.mem_ctrls0.num_writes::ruby.dir_cntrl0 60545
+system.mem_ctrls0.num_writes::total 60545
+system.mem_ctrls0.bw_read::ruby.dir_cntrl0 1866710
+system.mem_ctrls0.bw_read::total 1866710
+system.mem_ctrls0.bw_write::ruby.dir_cntrl0 1346549
+system.mem_ctrls0.bw_write::total 1346549
+system.mem_ctrls0.bw_total::ruby.dir_cntrl0 3213259
+system.mem_ctrls0.bw_total::total 3213259
+system.mem_ctrls0.readReqs 83933
+system.mem_ctrls0.writeReqs 60545
+system.mem_ctrls0.readBursts 83933
+system.mem_ctrls0.writeBursts 60545
+system.mem_ctrls0.bytesReadDRAM 5358464
+system.mem_ctrls0.bytesReadWrQ 13248
+system.mem_ctrls0.bytesWritten 3873728
+system.mem_ctrls0.bytesReadSys 5371712
+system.mem_ctrls0.bytesWrittenSys 3874880
+system.mem_ctrls0.servicedByWrQ 207
+system.mem_ctrls0.mergedWrBursts 0
+system.mem_ctrls0.neitherReadNorWriteReqs 0
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+system.mem_ctrls0.numRdRetry 0
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+system.mem_ctrls0.totGap 2877635963000
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+system.mem_ctrls0.wrQLenPdf::18 3401
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+system.mem_ctrls0.wrQLenPdf::24 3320
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+system.ruby.Store_Conditional.latency_hist_seqr | 0 0.00% 0.00% | 460413 100.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00%
+system.ruby.Store_Conditional.latency_hist_seqr::total 460413
+system.ruby.Store_Conditional.hit_latency_hist_seqr::bucket_size 1
+system.ruby.Store_Conditional.hit_latency_hist_seqr::max_bucket 9
+system.ruby.Store_Conditional.hit_latency_hist_seqr::samples 460413
+system.ruby.Store_Conditional.hit_latency_hist_seqr::mean 1
+system.ruby.Store_Conditional.hit_latency_hist_seqr::gmean 1
+system.ruby.Store_Conditional.hit_latency_hist_seqr | 0 0.00% 0.00% | 460413 100.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00%
+system.ruby.Store_Conditional.hit_latency_hist_seqr::total 460413
+system.ruby.Directory_Controller.GETX | 68292 49.99% 49.99% | 68325 50.01% 100.00%
+system.ruby.Directory_Controller.GETX::total 136617
+system.ruby.Directory_Controller.GETS | 15635 50.43% 50.43% | 15369 49.57% 100.00%
+system.ruby.Directory_Controller.GETS::total 31004
+system.ruby.Directory_Controller.PUTX | 42433 49.98% 49.98% | 42474 50.02% 100.00%
+system.ruby.Directory_Controller.PUTX::total 84907
+system.ruby.Directory_Controller.Unblock | 14793 50.38% 50.38% | 14567 49.62% 100.00%
+system.ruby.Directory_Controller.Unblock::total 29360
+system.ruby.Directory_Controller.Last_Unblock | 842 51.22% 51.22% | 802 48.78% 100.00%
+system.ruby.Directory_Controller.Last_Unblock::total 1644
+system.ruby.Directory_Controller.Exclusive_Unblock | 86404 49.99% 49.99% | 86437 50.01% 100.00%
+system.ruby.Directory_Controller.Exclusive_Unblock::total 172841
+system.ruby.Directory_Controller.Dirty_Writeback | 42433 49.98% 49.98% | 42474 50.02% 100.00%
+system.ruby.Directory_Controller.Dirty_Writeback::total 84907
+system.ruby.Directory_Controller.Memory_Data | 83933 50.07% 50.07% | 83701 49.93% 100.00%
+system.ruby.Directory_Controller.Memory_Data::total 167634
+system.ruby.Directory_Controller.Memory_Ack | 60545 49.98% 49.98% | 60586 50.02% 100.00%
+system.ruby.Directory_Controller.Memory_Ack::total 121131
+system.ruby.Directory_Controller.DMA_READ | 205 87.61% 87.61% | 29 12.39% 100.00%
+system.ruby.Directory_Controller.DMA_READ::total 234
+system.ruby.Directory_Controller.DMA_WRITE | 18112 50.00% 50.00% | 18112 50.00% 100.00%
+system.ruby.Directory_Controller.DMA_WRITE::total 36224
+system.ruby.Directory_Controller.DMA_ACK | 198 90.41% 90.41% | 21 9.59% 100.00%
+system.ruby.Directory_Controller.DMA_ACK::total 219
+system.ruby.Directory_Controller.Data | 2192 50.00% 50.00% | 2192 50.00% 100.00%
+system.ruby.Directory_Controller.Data::total 4384
+system.ruby.Directory_Controller.I.GETX | 64914 49.94% 49.94% | 65080 50.06% 100.00%
+system.ruby.Directory_Controller.I.GETX::total 129994
+system.ruby.Directory_Controller.I.GETS | 14793 50.38% 50.38% | 14567 49.62% 100.00%
+system.ruby.Directory_Controller.I.GETS::total 29360
+system.ruby.Directory_Controller.I.Memory_Ack | 42471 49.98% 49.98% | 42510 50.02% 100.00%
+system.ruby.Directory_Controller.I.Memory_Ack::total 84981
+system.ruby.Directory_Controller.I.DMA_READ | 6 46.15% 46.15% | 7 53.85% 100.00%
+system.ruby.Directory_Controller.I.DMA_READ::total 13
+system.ruby.Directory_Controller.I.DMA_WRITE | 15901 50.00% 50.00% | 15901 50.00% 100.00%
+system.ruby.Directory_Controller.I.DMA_WRITE::total 31802
+system.ruby.Directory_Controller.S.GETX | 3378 51.00% 51.00% | 3245 49.00% 100.00%
+system.ruby.Directory_Controller.S.GETX::total 6623
+system.ruby.Directory_Controller.S.GETS | 842 51.22% 51.22% | 802 48.78% 100.00%
+system.ruby.Directory_Controller.S.GETS::total 1644
+system.ruby.Directory_Controller.S.DMA_READ | 1 50.00% 50.00% | 1 50.00% 100.00%
+system.ruby.Directory_Controller.S.DMA_READ::total 2
+system.ruby.Directory_Controller.S.DMA_WRITE | 19 50.00% 50.00% | 19 50.00% 100.00%
+system.ruby.Directory_Controller.S.DMA_WRITE::total 38
+system.ruby.Directory_Controller.M.PUTX | 42433 49.98% 49.98% | 42474 50.02% 100.00%
+system.ruby.Directory_Controller.M.PUTX::total 84907
+system.ruby.Directory_Controller.M.DMA_READ | 198 90.41% 90.41% | 21 9.59% 100.00%
+system.ruby.Directory_Controller.M.DMA_READ::total 219
+system.ruby.Directory_Controller.M.DMA_WRITE | 2192 50.00% 50.00% | 2192 50.00% 100.00%
+system.ruby.Directory_Controller.M.DMA_WRITE::total 4384
+system.ruby.Directory_Controller.IS.Unblock | 14793 50.38% 50.38% | 14567 49.62% 100.00%
+system.ruby.Directory_Controller.IS.Unblock::total 29360
+system.ruby.Directory_Controller.IS.Memory_Data | 14793 50.38% 50.38% | 14567 49.62% 100.00%
+system.ruby.Directory_Controller.IS.Memory_Data::total 29360
+system.ruby.Directory_Controller.SS.Last_Unblock | 842 51.22% 51.22% | 802 48.78% 100.00%
+system.ruby.Directory_Controller.SS.Last_Unblock::total 1644
+system.ruby.Directory_Controller.SS.Memory_Data | 842 51.22% 51.22% | 802 48.78% 100.00%
+system.ruby.Directory_Controller.SS.Memory_Data::total 1644
+system.ruby.Directory_Controller.MM.Exclusive_Unblock | 68292 49.99% 49.99% | 68325 50.01% 100.00%
+system.ruby.Directory_Controller.MM.Exclusive_Unblock::total 136617
+system.ruby.Directory_Controller.MM.Memory_Data | 68292 49.99% 49.99% | 68325 50.01% 100.00%
+system.ruby.Directory_Controller.MM.Memory_Data::total 136617
+system.ruby.Directory_Controller.MI.Dirty_Writeback | 42433 49.98% 49.98% | 42474 50.02% 100.00%
+system.ruby.Directory_Controller.MI.Dirty_Writeback::total 84907
+system.ruby.Directory_Controller.XI_M.Memory_Data | 6 46.15% 46.15% | 7 53.85% 100.00%
+system.ruby.Directory_Controller.XI_M.Memory_Data::total 13
+system.ruby.Directory_Controller.XI_U.Exclusive_Unblock | 18112 50.00% 50.00% | 18112 50.00% 100.00%
+system.ruby.Directory_Controller.XI_U.Exclusive_Unblock::total 36224
+system.ruby.Directory_Controller.XI_U.Memory_Ack | 18074 50.00% 50.00% | 18076 50.00% 100.00%
+system.ruby.Directory_Controller.XI_U.Memory_Ack::total 36150
+system.ruby.Directory_Controller.OI_D.Data | 2192 50.00% 50.00% | 2192 50.00% 100.00%
+system.ruby.Directory_Controller.OI_D.Data::total 4384
+system.ruby.Directory_Controller.MD.DMA_ACK | 198 90.41% 90.41% | 21 9.59% 100.00%
+system.ruby.Directory_Controller.MD.DMA_ACK::total 219
+system.ruby.DMA_Controller.ReadRequest | 0 0.00% 0.00% | 0 0.00% 0.00% | 0 0.00% 0.00% | 354 100.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00%
+system.ruby.DMA_Controller.ReadRequest::total 354
+system.ruby.DMA_Controller.WriteRequest | 0 0.00% 0.00% | 0 0.00% 0.00% | 0 0.00% 0.00% | 1082520 100.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00%
+system.ruby.DMA_Controller.WriteRequest::total 1082520
+system.ruby.DMA_Controller.Data | 0 0.00% 0.00% | 0 0.00% 0.00% | 0 0.00% 0.00% | 234 100.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00%
+system.ruby.DMA_Controller.Data::total 234
+system.ruby.DMA_Controller.DMA_Ack | 0 0.00% 0.00% | 0 0.00% 0.00% | 0 0.00% 0.00% | 36224 100.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00%
+system.ruby.DMA_Controller.DMA_Ack::total 36224
+system.ruby.DMA_Controller.Inv_Ack | 0 0.00% 0.00% | 0 0.00% 0.00% | 0 0.00% 0.00% | 38 100.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00%
+system.ruby.DMA_Controller.Inv_Ack::total 38
+system.ruby.DMA_Controller.All_Acks | 0 0.00% 0.00% | 0 0.00% 0.00% | 0 0.00% 0.00% | 36224 100.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00%
+system.ruby.DMA_Controller.All_Acks::total 36224
+system.ruby.DMA_Controller.READY.ReadRequest | 0 0.00% 0.00% | 0 0.00% 0.00% | 0 0.00% 0.00% | 234 100.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00%
+system.ruby.DMA_Controller.READY.ReadRequest::total 234
+system.ruby.DMA_Controller.READY.WriteRequest | 0 0.00% 0.00% | 0 0.00% 0.00% | 0 0.00% 0.00% | 36224 100.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00%
+system.ruby.DMA_Controller.READY.WriteRequest::total 36224
+system.ruby.DMA_Controller.BUSY_RD.ReadRequest | 0 0.00% 0.00% | 0 0.00% 0.00% | 0 0.00% 0.00% | 120 100.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00%
+system.ruby.DMA_Controller.BUSY_RD.ReadRequest::total 120
+system.ruby.DMA_Controller.BUSY_RD.Data | 0 0.00% 0.00% | 0 0.00% 0.00% | 0 0.00% 0.00% | 234 100.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00%
+system.ruby.DMA_Controller.BUSY_RD.Data::total 234
+system.ruby.DMA_Controller.BUSY_WR.WriteRequest | 0 0.00% 0.00% | 0 0.00% 0.00% | 0 0.00% 0.00% | 1046296 100.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00%
+system.ruby.DMA_Controller.BUSY_WR.WriteRequest::total 1046296
+system.ruby.DMA_Controller.BUSY_WR.DMA_Ack | 0 0.00% 0.00% | 0 0.00% 0.00% | 0 0.00% 0.00% | 36224 100.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00%
+system.ruby.DMA_Controller.BUSY_WR.DMA_Ack::total 36224
+system.ruby.DMA_Controller.BUSY_WR.Inv_Ack | 0 0.00% 0.00% | 0 0.00% 0.00% | 0 0.00% 0.00% | 38 100.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00%
+system.ruby.DMA_Controller.BUSY_WR.Inv_Ack::total 38
+system.ruby.DMA_Controller.BUSY_WR.All_Acks | 0 0.00% 0.00% | 0 0.00% 0.00% | 0 0.00% 0.00% | 36224 100.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00%
+system.ruby.DMA_Controller.BUSY_WR.All_Acks::total 36224
+system.ruby.L1Cache_Controller.Load 24230106 0.00% 0.00%
+system.ruby.L1Cache_Controller.Ifetch 115772647 0.00% 0.00%
+system.ruby.L1Cache_Controller.Store 20058528 0.00% 0.00%
+system.ruby.L1Cache_Controller.L1_Replacement 2437124 0.00% 0.00%
+system.ruby.L1Cache_Controller.Fwd_GETX 13 0.00% 0.00%
+system.ruby.L1Cache_Controller.Fwd_DMA 170 0.00% 0.00%
+system.ruby.L1Cache_Controller.Inv 15 0.00% 0.00%
+system.ruby.L1Cache_Controller.Data 1742675 0.00% 0.00%
+system.ruby.L1Cache_Controller.Exclusive_Data 695119 0.00% 0.00%
+system.ruby.L1Cache_Controller.Writeback_Ack 1710696 0.00% 0.00%
+system.ruby.L1Cache_Controller.Writeback_Ack_Data 723019 0.00% 0.00%
+system.ruby.L1Cache_Controller.All_acks 306547 0.00% 0.00%
+system.ruby.L1Cache_Controller.Use_Timeout 695119 0.00% 0.00%
+system.ruby.L1Cache_Controller.I.Load 599377 0.00% 0.00%
+system.ruby.L1Cache_Controller.I.Ifetch 1531870 0.00% 0.00%
+system.ruby.L1Cache_Controller.I.Store 303505 0.00% 0.00%
+system.ruby.L1Cache_Controller.I.L1_Replacement 12 0.00% 0.00%
+system.ruby.L1Cache_Controller.S.Load 2005001 0.00% 0.00%
+system.ruby.L1Cache_Controller.S.Ifetch 113621133 0.00% 0.00%
+system.ruby.L1Cache_Controller.S.Store 3042 0.00% 0.00%
+system.ruby.L1Cache_Controller.S.L1_Replacement 1738970 0.00% 0.00%
+system.ruby.L1Cache_Controller.S.Inv 15 0.00% 0.00%
+system.ruby.L1Cache_Controller.M.Load 8042001 0.00% 0.00%
+system.ruby.L1Cache_Controller.M.Ifetch 379575 0.00% 0.00%
+system.ruby.L1Cache_Controller.M.Store 92926 0.00% 0.00%
+system.ruby.L1Cache_Controller.M.L1_Replacement 187860 0.00% 0.00%
+system.ruby.L1Cache_Controller.M_W.Load 202674 0.00% 0.00%
+system.ruby.L1Cache_Controller.M_W.Ifetch 61597 0.00% 0.00%
+system.ruby.L1Cache_Controller.M_W.Store 107662 0.00% 0.00%
+system.ruby.L1Cache_Controller.M_W.L1_Replacement 3396 0.00% 0.00%
+system.ruby.L1Cache_Controller.M_W.Use_Timeout 280910 0.00% 0.00%
+system.ruby.L1Cache_Controller.MM.Load 13163880 0.00% 0.00%
+system.ruby.L1Cache_Controller.MM.Store 16598991 0.00% 0.00%
+system.ruby.L1Cache_Controller.MM.L1_Replacement 506886 0.00% 0.00%
+system.ruby.L1Cache_Controller.MM.Fwd_GETX 13 0.00% 0.00%
+system.ruby.L1Cache_Controller.MM.Fwd_DMA 170 0.00% 0.00%
+system.ruby.L1Cache_Controller.MM_W.Load 48742 0.00% 0.00%
+system.ruby.L1Cache_Controller.MM_W.Store 2952384 0.00% 0.00%
+system.ruby.L1Cache_Controller.MM_W.Use_Timeout 414209 0.00% 0.00%
+system.ruby.L1Cache_Controller.IM.Exclusive_Data 303505 0.00% 0.00%
+system.ruby.L1Cache_Controller.SM.Exclusive_Data 3042 0.00% 0.00%
+system.ruby.L1Cache_Controller.OM.All_acks 306547 0.00% 0.00%
+system.ruby.L1Cache_Controller.IS.Data 1742675 0.00% 0.00%
+system.ruby.L1Cache_Controller.IS.Exclusive_Data 388572 0.00% 0.00%
+system.ruby.L1Cache_Controller.SI.Load 167673 0.00% 0.00%
+system.ruby.L1Cache_Controller.SI.Ifetch 177752 0.00% 0.00%
+system.ruby.L1Cache_Controller.SI.Store 18 0.00% 0.00%
+system.ruby.L1Cache_Controller.SI.Writeback_Ack 1710696 0.00% 0.00%
+system.ruby.L1Cache_Controller.SI.Writeback_Ack_Data 28273 0.00% 0.00%
+system.ruby.L1Cache_Controller.MI.Load 758 0.00% 0.00%
+system.ruby.L1Cache_Controller.MI.Ifetch 720 0.00% 0.00%
+system.ruby.L1Cache_Controller.MI.Writeback_Ack_Data 694746 0.00% 0.00%
+system.ruby.L2Cache_Controller.L1_GETS 2131540 0.00% 0.00%
+system.ruby.L2Cache_Controller.L1_GETX 306547 0.00% 0.00%
+system.ruby.L2Cache_Controller.L1_PUTX 694746 0.00% 0.00%
+system.ruby.L2Cache_Controller.L1_PUTS_only 1738970 0.00% 0.00%
+system.ruby.L2Cache_Controller.L1_PUTS 2 0.00% 0.00%
+system.ruby.L2Cache_Controller.Fwd_GETX 4384 0.00% 0.00%
+system.ruby.L2Cache_Controller.Fwd_DMA 219 0.00% 0.00%
+system.ruby.L2Cache_Controller.Inv 38 0.00% 0.00%
+system.ruby.L2Cache_Controller.IntAck 15 0.00% 0.00%
+system.ruby.L2Cache_Controller.All_Acks 136632 0.00% 0.00%
+system.ruby.L2Cache_Controller.Data 167621 0.00% 0.00%
+system.ruby.L2Cache_Controller.Data_Exclusive 13 0.00% 0.00%
+system.ruby.L2Cache_Controller.L1_WBCLEANDATA 28273 0.00% 0.00%
+system.ruby.L2Cache_Controller.L1_WBDIRTYDATA 694746 0.00% 0.00%
+system.ruby.L2Cache_Controller.Writeback_Ack 84907 0.00% 0.00%
+system.ruby.L2Cache_Controller.Unblock 3453370 0.00% 0.00%
+system.ruby.L2Cache_Controller.Exclusive_Unblock 695119 0.00% 0.00%
+system.ruby.L2Cache_Controller.DmaAck 170 0.00% 0.00%
+system.ruby.L2Cache_Controller.L2_Replacement 92511 0.00% 0.00%
+system.ruby.L2Cache_Controller.NP.L1_GETS 30988 0.00% 0.00%
+system.ruby.L2Cache_Controller.NP.L1_GETX 131317 0.00% 0.00%
+system.ruby.L2Cache_Controller.I.L1_GETS 16 0.00% 0.00%
+system.ruby.L2Cache_Controller.ILS.L1_GETX 2718 0.00% 0.00%
+system.ruby.L2Cache_Controller.ILS.L1_PUTS_only 28273 0.00% 0.00%
+system.ruby.L2Cache_Controller.ILS.Inv 15 0.00% 0.00%
+system.ruby.L2Cache_Controller.ILX.L1_PUTX 694746 0.00% 0.00%
+system.ruby.L2Cache_Controller.ILX.Fwd_GETX 13 0.00% 0.00%
+system.ruby.L2Cache_Controller.ILX.Fwd_DMA 170 0.00% 0.00%
+system.ruby.L2Cache_Controller.S.L1_GETS 1711671 0.00% 0.00%
+system.ruby.L2Cache_Controller.S.L1_GETX 2258 0.00% 0.00%
+system.ruby.L2Cache_Controller.S.Inv 23 0.00% 0.00%
+system.ruby.L2Cache_Controller.S.L2_Replacement 7601 0.00% 0.00%
+system.ruby.L2Cache_Controller.SLS.L1_GETX 324 0.00% 0.00%
+system.ruby.L2Cache_Controller.SLS.L1_PUTS_only 1710697 0.00% 0.00%
+system.ruby.L2Cache_Controller.SLS.L2_Replacement 3 0.00% 0.00%
+system.ruby.L2Cache_Controller.M.L1_GETS 388572 0.00% 0.00%
+system.ruby.L2Cache_Controller.M.L1_GETX 169930 0.00% 0.00%
+system.ruby.L2Cache_Controller.M.Fwd_GETX 4371 0.00% 0.00%
+system.ruby.L2Cache_Controller.M.Fwd_DMA 49 0.00% 0.00%
+system.ruby.L2Cache_Controller.M.L2_Replacement 84907 0.00% 0.00%
+system.ruby.L2Cache_Controller.IFGX.Data_Exclusive 13 0.00% 0.00%
+system.ruby.L2Cache_Controller.IW.L1_WBCLEANDATA 28273 0.00% 0.00%
+system.ruby.L2Cache_Controller.SW.L1_GETS 293 0.00% 0.00%
+system.ruby.L2Cache_Controller.SW.Unblock 1710696 0.00% 0.00%
+system.ruby.L2Cache_Controller.ILXW.L1_WBDIRTYDATA 694746 0.00% 0.00%
+system.ruby.L2Cache_Controller.IGS.Data 31004 0.00% 0.00%
+system.ruby.L2Cache_Controller.IGS.Unblock 31004 0.00% 0.00%
+system.ruby.L2Cache_Controller.IGM.Data 133575 0.00% 0.00%
+system.ruby.L2Cache_Controller.IGMLS.Data 3042 0.00% 0.00%
+system.ruby.L2Cache_Controller.IGMO.All_Acks 136617 0.00% 0.00%
+system.ruby.L2Cache_Controller.IGMO.Exclusive_Unblock 136617 0.00% 0.00%
+system.ruby.L2Cache_Controller.II.IntAck 15 0.00% 0.00%
+system.ruby.L2Cache_Controller.II.All_Acks 15 0.00% 0.00%
+system.ruby.L2Cache_Controller.MM.Exclusive_Unblock 169930 0.00% 0.00%
+system.ruby.L2Cache_Controller.SS.L1_PUTS 2 0.00% 0.00%
+system.ruby.L2Cache_Controller.SS.Unblock 1711670 0.00% 0.00%
+system.ruby.L2Cache_Controller.OO.Exclusive_Unblock 388572 0.00% 0.00%
+system.ruby.L2Cache_Controller.MI.Writeback_Ack 84907 0.00% 0.00%
+system.ruby.L2Cache_Controller.ILXD.DmaAck 170 0.00% 0.00%
+
+---------- End Simulation Statistics ----------
--- /dev/null
+
+---------- Begin Simulation Statistics ----------
+sim_seconds 47.701968
+sim_ticks 47701967881000
+final_tick 47701967881000
+sim_freq 1000000000000
+host_inst_rate 169263
+host_op_rate 201687
+host_tick_rate 9441246628
+host_mem_usage 1351660
+host_seconds 5052.51
+sim_insts 855204516
+sim_ops 1019023572
+system.voltage_domain.voltage 1
+system.clk_domain.clock 1000
+system.mem_ctrls0.pwrStateResidencyTicks::UNDEFINED 47701967881000
+system.mem_ctrls0.bytes_read::ruby.dir_cntrl0 60133632
+system.mem_ctrls0.bytes_read::total 60133632
+system.mem_ctrls0.bytes_written::ruby.dir_cntrl0 45711488
+system.mem_ctrls0.bytes_written::total 45711488
+system.mem_ctrls0.num_reads::ruby.dir_cntrl0 939588
+system.mem_ctrls0.num_reads::total 939588
+system.mem_ctrls0.num_writes::ruby.dir_cntrl0 714242
+system.mem_ctrls0.num_writes::total 714242
+system.mem_ctrls0.bw_read::ruby.dir_cntrl0 1260611
+system.mem_ctrls0.bw_read::total 1260611
+system.mem_ctrls0.bw_write::ruby.dir_cntrl0 958273
+system.mem_ctrls0.bw_write::total 958273
+system.mem_ctrls0.bw_total::ruby.dir_cntrl0 2218884
+system.mem_ctrls0.bw_total::total 2218884
+system.mem_ctrls0.readReqs 939588
+system.mem_ctrls0.writeReqs 714242
+system.mem_ctrls0.readBursts 939588
+system.mem_ctrls0.writeBursts 714242
+system.mem_ctrls0.bytesReadDRAM 60043648
+system.mem_ctrls0.bytesReadWrQ 89984
+system.mem_ctrls0.bytesWritten 45709184
+system.mem_ctrls0.bytesReadSys 60133632
+system.mem_ctrls0.bytesWrittenSys 45711488
+system.mem_ctrls0.servicedByWrQ 1406
+system.mem_ctrls0.mergedWrBursts 6
+system.mem_ctrls0.neitherReadNorWriteReqs 0
+system.mem_ctrls0.perBankRdBursts::0 53584
+system.mem_ctrls0.perBankRdBursts::1 60253
+system.mem_ctrls0.perBankRdBursts::2 66103
+system.mem_ctrls0.perBankRdBursts::3 60855
+system.mem_ctrls0.perBankRdBursts::4 61195
+system.mem_ctrls0.perBankRdBursts::5 63337
+system.mem_ctrls0.perBankRdBursts::6 56073
+system.mem_ctrls0.perBankRdBursts::7 58711
+system.mem_ctrls0.perBankRdBursts::8 59012
+system.mem_ctrls0.perBankRdBursts::9 54132
+system.mem_ctrls0.perBankRdBursts::10 58324
+system.mem_ctrls0.perBankRdBursts::11 62353
+system.mem_ctrls0.perBankRdBursts::12 60538
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+system.ruby.Directory_Controller.S.DMA_WRITE | 187 45.28% 45.28% | 226 54.72% 100.00%
+system.ruby.Directory_Controller.S.DMA_WRITE::total 413
+system.ruby.Directory_Controller.M.PUTX | 660729 50.23% 50.23% | 654766 49.77% 100.00%
+system.ruby.Directory_Controller.M.PUTX::total 1315495
+system.ruby.Directory_Controller.M.PUTO_SHARERS | 18 46.15% 46.15% | 21 53.85% 100.00%
+system.ruby.Directory_Controller.M.PUTO_SHARERS::total 39
+system.ruby.Directory_Controller.M.DMA_READ | 1558 69.68% 69.68% | 678 30.32% 100.00%
+system.ruby.Directory_Controller.M.DMA_READ::total 2236
+system.ruby.Directory_Controller.M.DMA_WRITE | 13410 49.88% 49.88% | 13476 50.12% 100.00%
+system.ruby.Directory_Controller.M.DMA_WRITE::total 26886
+system.ruby.Directory_Controller.IS.Unblock | 157675 52.25% 52.25% | 144082 47.75% 100.00%
+system.ruby.Directory_Controller.IS.Unblock::total 301757
+system.ruby.Directory_Controller.IS.Memory_Data | 157676 52.25% 52.25% | 144082 47.75% 100.00%
+system.ruby.Directory_Controller.IS.Memory_Data::total 301758
+system.ruby.Directory_Controller.IS.Memory_Ack | 1 100.00% 100.00% | 0 0.00% 100.00%
+system.ruby.Directory_Controller.IS.Memory_Ack::total 1
+system.ruby.Directory_Controller.SS.Last_Unblock | 87343 50.97% 50.97% | 84025 49.03% 100.00%
+system.ruby.Directory_Controller.SS.Last_Unblock::total 171368
+system.ruby.Directory_Controller.SS.Memory_Data | 87343 50.97% 50.97% | 84025 49.03% 100.00%
+system.ruby.Directory_Controller.SS.Memory_Data::total 171368
+system.ruby.Directory_Controller.MM.Exclusive_Unblock | 691418 50.21% 50.21% | 685568 49.79% 100.00%
+system.ruby.Directory_Controller.MM.Exclusive_Unblock::total 1376986
+system.ruby.Directory_Controller.MM.Memory_Data | 691418 50.21% 50.21% | 685568 49.79% 100.00%
+system.ruby.Directory_Controller.MM.Memory_Data::total 1376986
+system.ruby.Directory_Controller.MI.Dirty_Writeback | 660729 50.23% 50.23% | 654766 49.77% 100.00%
+system.ruby.Directory_Controller.MI.Dirty_Writeback::total 1315495
+system.ruby.Directory_Controller.MI.DMA_WRITE | 2 100.00% 100.00% | 0 0.00% 100.00%
+system.ruby.Directory_Controller.MI.DMA_WRITE::total 2
+system.ruby.Directory_Controller.MIS.Dirty_Writeback | 18 46.15% 46.15% | 21 53.85% 100.00%
+system.ruby.Directory_Controller.MIS.Dirty_Writeback::total 39
+system.ruby.Directory_Controller.XI_M.Memory_Data | 3151 50.05% 50.05% | 3145 49.95% 100.00%
+system.ruby.Directory_Controller.XI_M.Memory_Data::total 6296
+system.ruby.Directory_Controller.XI_U.Exclusive_Unblock | 53495 50.00% 50.00% | 53492 50.00% 100.00%
+system.ruby.Directory_Controller.XI_U.Exclusive_Unblock::total 106987
+system.ruby.Directory_Controller.XI_U.Memory_Ack | 53371 49.99% 49.99% | 53384 50.01% 100.00%
+system.ruby.Directory_Controller.XI_U.Memory_Ack::total 106755
+system.ruby.Directory_Controller.OI_D.Data | 13410 49.88% 49.88% | 13476 50.12% 100.00%
+system.ruby.Directory_Controller.OI_D.Data::total 26886
+system.ruby.Directory_Controller.MD.DMA_ACK | 1558 69.68% 69.68% | 678 30.32% 100.00%
+system.ruby.Directory_Controller.MD.DMA_ACK::total 2236
+system.ruby.DMA_Controller.ReadRequest | 0 0.00% 0.00% | 0 0.00% 0.00% | 0 0.00% 0.00% | 250301 99.92% 99.92% | 202 0.08% 100.00% | 0 0.00% 100.00%
+system.ruby.DMA_Controller.ReadRequest::total 250503
+system.ruby.DMA_Controller.WriteRequest | 0 0.00% 0.00% | 0 0.00% 0.00% | 0 0.00% 0.00% | 3309822 100.00% 100.00% | 3 0.00% 100.00% | 0 0.00% 100.00%
+system.ruby.DMA_Controller.WriteRequest::total 3309825
+system.ruby.DMA_Controller.Data | 0 0.00% 0.00% | 0 0.00% 0.00% | 0 0.00% 0.00% | 8894 99.59% 99.59% | 37 0.41% 100.00% | 0 0.00% 100.00%
+system.ruby.DMA_Controller.Data::total 8931
+system.ruby.DMA_Controller.DMA_Ack | 0 0.00% 0.00% | 0 0.00% 0.00% | 0 0.00% 0.00% | 106984 100.00% 100.00% | 3 0.00% 100.00% | 0 0.00% 100.00%
+system.ruby.DMA_Controller.DMA_Ack::total 106987
+system.ruby.DMA_Controller.Inv_Ack | 0 0.00% 0.00% | 0 0.00% 0.00% | 0 0.00% 0.00% | 413 100.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00%
+system.ruby.DMA_Controller.Inv_Ack::total 413
+system.ruby.DMA_Controller.All_Acks | 0 0.00% 0.00% | 0 0.00% 0.00% | 0 0.00% 0.00% | 106984 100.00% 100.00% | 3 0.00% 100.00% | 0 0.00% 100.00%
+system.ruby.DMA_Controller.All_Acks::total 106987
+system.ruby.DMA_Controller.READY.ReadRequest | 0 0.00% 0.00% | 0 0.00% 0.00% | 0 0.00% 0.00% | 8894 99.59% 99.59% | 37 0.41% 100.00% | 0 0.00% 100.00%
+system.ruby.DMA_Controller.READY.ReadRequest::total 8931
+system.ruby.DMA_Controller.READY.WriteRequest | 0 0.00% 0.00% | 0 0.00% 0.00% | 0 0.00% 0.00% | 106984 100.00% 100.00% | 3 0.00% 100.00% | 0 0.00% 100.00%
+system.ruby.DMA_Controller.READY.WriteRequest::total 106987
+system.ruby.DMA_Controller.BUSY_RD.ReadRequest | 0 0.00% 0.00% | 0 0.00% 0.00% | 0 0.00% 0.00% | 241407 99.93% 99.93% | 165 0.07% 100.00% | 0 0.00% 100.00%
+system.ruby.DMA_Controller.BUSY_RD.ReadRequest::total 241572
+system.ruby.DMA_Controller.BUSY_RD.Data | 0 0.00% 0.00% | 0 0.00% 0.00% | 0 0.00% 0.00% | 8894 99.59% 99.59% | 37 0.41% 100.00% | 0 0.00% 100.00%
+system.ruby.DMA_Controller.BUSY_RD.Data::total 8931
+system.ruby.DMA_Controller.BUSY_WR.WriteRequest | 0 0.00% 0.00% | 0 0.00% 0.00% | 0 0.00% 0.00% | 3202838 100.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00%
+system.ruby.DMA_Controller.BUSY_WR.WriteRequest::total 3202838
+system.ruby.DMA_Controller.BUSY_WR.DMA_Ack | 0 0.00% 0.00% | 0 0.00% 0.00% | 0 0.00% 0.00% | 106984 100.00% 100.00% | 3 0.00% 100.00% | 0 0.00% 100.00%
+system.ruby.DMA_Controller.BUSY_WR.DMA_Ack::total 106987
+system.ruby.DMA_Controller.BUSY_WR.Inv_Ack | 0 0.00% 0.00% | 0 0.00% 0.00% | 0 0.00% 0.00% | 413 100.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00%
+system.ruby.DMA_Controller.BUSY_WR.Inv_Ack::total 413
+system.ruby.DMA_Controller.BUSY_WR.All_Acks | 0 0.00% 0.00% | 0 0.00% 0.00% | 0 0.00% 0.00% | 106984 100.00% 100.00% | 3 0.00% 100.00% | 0 0.00% 100.00%
+system.ruby.DMA_Controller.BUSY_WR.All_Acks::total 106987
+system.ruby.L1Cache_Controller.Load | 93672271 54.53% 54.53% | 78099262 45.47% 100.00%
+system.ruby.L1Cache_Controller.Load::total 171771533
+system.ruby.L1Cache_Controller.Ifetch | 472009619 55.15% 55.15% | 383825779 44.85% 100.00%
+system.ruby.L1Cache_Controller.Ifetch::total 855835398
+system.ruby.L1Cache_Controller.Store | 89261373 54.72% 54.72% | 73866508 45.28% 100.00%
+system.ruby.L1Cache_Controller.Store::total 163127881
+system.ruby.L1Cache_Controller.L1_Replacement | 11613388 54.55% 54.55% | 9676755 45.45% 100.00%
+system.ruby.L1Cache_Controller.L1_Replacement::total 21290143
+system.ruby.L1Cache_Controller.Own_GETX | 1536 50.23% 50.23% | 1522 49.77% 100.00%
+system.ruby.L1Cache_Controller.Own_GETX::total 3058
+system.ruby.L1Cache_Controller.Fwd_GETX | 57472 52.69% 52.69% | 51613 47.31% 100.00%
+system.ruby.L1Cache_Controller.Fwd_GETX::total 109085
+system.ruby.L1Cache_Controller.Fwd_GETS | 145222 48.78% 48.78% | 152500 51.22% 100.00%
+system.ruby.L1Cache_Controller.Fwd_GETS::total 297722
+system.ruby.L1Cache_Controller.Fwd_DMA | 569 57.19% 57.19% | 426 42.81% 100.00%
+system.ruby.L1Cache_Controller.Fwd_DMA::total 995
+system.ruby.L1Cache_Controller.Inv | 2626 48.33% 48.33% | 2808 51.67% 100.00%
+system.ruby.L1Cache_Controller.Inv::total 5434
+system.ruby.L1Cache_Controller.Ack | 54505 47.53% 47.53% | 60164 52.47% 100.00%
+system.ruby.L1Cache_Controller.Ack::total 114669
+system.ruby.L1Cache_Controller.Data | 6875924 52.70% 52.70% | 6170294 47.30% 100.00%
+system.ruby.L1Cache_Controller.Data::total 13046218
+system.ruby.L1Cache_Controller.Exclusive_Data | 4898127 57.38% 57.38% | 3637556 42.62% 100.00%
+system.ruby.L1Cache_Controller.Exclusive_Data::total 8535683
+system.ruby.L1Cache_Controller.Writeback_Ack | 6574964 52.61% 52.61% | 5923695 47.39% 100.00%
+system.ruby.L1Cache_Controller.Writeback_Ack::total 12498659
+system.ruby.L1Cache_Controller.Writeback_Ack_Data | 4941903 57.31% 57.31% | 3681780 42.69% 100.00%
+system.ruby.L1Cache_Controller.Writeback_Ack_Data::total 8623683
+system.ruby.L1Cache_Controller.Writeback_Nack | 2 66.67% 66.67% | 1 33.33% 100.00%
+system.ruby.L1Cache_Controller.Writeback_Nack::total 3
+system.ruby.L1Cache_Controller.All_acks | 2395111 59.49% 59.49% | 1630974 40.51% 100.00%
+system.ruby.L1Cache_Controller.All_acks::total 4026085
+system.ruby.L1Cache_Controller.Use_Timeout | 4899662 57.38% 57.38% | 3639078 42.62% 100.00%
+system.ruby.L1Cache_Controller.Use_Timeout::total 8538740
+system.ruby.L1Cache_Controller.I.Load | 4014305 54.73% 54.73% | 3321076 45.27% 100.00%
+system.ruby.L1Cache_Controller.I.Load::total 7335381
+system.ruby.L1Cache_Controller.I.Ifetch | 5366172 52.49% 52.49% | 4857322 47.51% 100.00%
+system.ruby.L1Cache_Controller.I.Ifetch::total 10223494
+system.ruby.L1Cache_Controller.I.Store | 2275464 59.45% 59.45% | 1551875 40.55% 100.00%
+system.ruby.L1Cache_Controller.I.Store::total 3827339
+system.ruby.L1Cache_Controller.I.L1_Replacement | 96510 57.52% 57.52% | 71277 42.48% 100.00%
+system.ruby.L1Cache_Controller.I.L1_Replacement::total 167787
+system.ruby.L1Cache_Controller.S.Load | 12058362 53.08% 53.08% | 10658255 46.92% 100.00%
+system.ruby.L1Cache_Controller.S.Load::total 22716617
+system.ruby.L1Cache_Controller.S.Ifetch | 466637721 55.18% 55.18% | 378967131 44.82% 100.00%
+system.ruby.L1Cache_Controller.S.Ifetch::total 845604852
+system.ruby.L1Cache_Controller.S.Store | 118110 60.36% 60.36% | 77572 39.64% 100.00%
+system.ruby.L1Cache_Controller.S.Store::total 195682
+system.ruby.L1Cache_Controller.S.L1_Replacement | 6754604 52.59% 52.59% | 6089329 47.41% 100.00%
+system.ruby.L1Cache_Controller.S.L1_Replacement::total 12843933
+system.ruby.L1Cache_Controller.S.Fwd_GETS | 2238 42.24% 42.24% | 3060 57.76% 100.00%
+system.ruby.L1Cache_Controller.S.Fwd_GETS::total 5298
+system.ruby.L1Cache_Controller.S.Inv | 2622 48.31% 48.31% | 2806 51.69% 100.00%
+system.ruby.L1Cache_Controller.S.Inv::total 5428
+system.ruby.L1Cache_Controller.O.Load | 266729 48.34% 48.34% | 285028 51.66% 100.00%
+system.ruby.L1Cache_Controller.O.Load::total 551757
+system.ruby.L1Cache_Controller.O.Store | 1537 50.16% 50.16% | 1527 49.84% 100.00%
+system.ruby.L1Cache_Controller.O.Store::total 3064
+system.ruby.L1Cache_Controller.O.L1_Replacement | 27965 46.61% 46.61% | 32033 53.39% 100.00%
+system.ruby.L1Cache_Controller.O.L1_Replacement::total 59998
+system.ruby.L1Cache_Controller.O.Fwd_GETX | 14380 44.27% 44.27% | 18102 55.73% 100.00%
+system.ruby.L1Cache_Controller.O.Fwd_GETX::total 32482
+system.ruby.L1Cache_Controller.O.Fwd_GETS | 18863 41.80% 41.80% | 26263 58.20% 100.00%
+system.ruby.L1Cache_Controller.O.Fwd_GETS::total 45126
+system.ruby.L1Cache_Controller.M.Load | 11815755 57.14% 57.14% | 8864201 42.86% 100.00%
+system.ruby.L1Cache_Controller.M.Load::total 20679956
+system.ruby.L1Cache_Controller.M.Store | 661017 54.08% 54.08% | 561249 45.92% 100.00%
+system.ruby.L1Cache_Controller.M.Store::total 1222266
+system.ruby.L1Cache_Controller.M.L1_Replacement | 1318265 57.42% 57.42% | 977394 42.58% 100.00%
+system.ruby.L1Cache_Controller.M.L1_Replacement::total 2295659
+system.ruby.L1Cache_Controller.M.Fwd_GETX | 3703 48.47% 48.47% | 3937 51.53% 100.00%
+system.ruby.L1Cache_Controller.M.Fwd_GETX::total 7640
+system.ruby.L1Cache_Controller.M.Fwd_GETS | 43887 45.93% 45.93% | 51664 54.07% 100.00%
+system.ruby.L1Cache_Controller.M.Fwd_GETS::total 95551
+system.ruby.L1Cache_Controller.M_W.Load | 1121024 57.47% 57.47% | 829567 42.53% 100.00%
+system.ruby.L1Cache_Controller.M_W.Load::total 1950591
+system.ruby.L1Cache_Controller.M_W.Ifetch | 13 65.00% 65.00% | 7 35.00% 100.00%
+system.ruby.L1Cache_Controller.M_W.Ifetch::total 20
+system.ruby.L1Cache_Controller.M_W.Store | 477638 53.58% 53.58% | 413796 46.42% 100.00%
+system.ruby.L1Cache_Controller.M_W.Store::total 891434
+system.ruby.L1Cache_Controller.M_W.L1_Replacement | 5 83.33% 83.33% | 1 16.67% 100.00%
+system.ruby.L1Cache_Controller.M_W.L1_Replacement::total 6
+system.ruby.L1Cache_Controller.M_W.Fwd_GETX | 630 57.22% 57.22% | 471 42.78% 100.00%
+system.ruby.L1Cache_Controller.M_W.Fwd_GETX::total 1101
+system.ruby.L1Cache_Controller.M_W.Fwd_GETS | 427 47.82% 47.82% | 466 52.18% 100.00%
+system.ruby.L1Cache_Controller.M_W.Fwd_GETS::total 893
+system.ruby.L1Cache_Controller.M_W.Use_Timeout | 2026913 55.97% 55.97% | 1594308 44.03% 100.00%
+system.ruby.L1Cache_Controller.M_W.Use_Timeout::total 3621221
+system.ruby.L1Cache_Controller.MM.Load | 64125299 54.32% 54.32% | 53925291 45.68% 100.00%
+system.ruby.L1Cache_Controller.MM.Load::total 118050590
+system.ruby.L1Cache_Controller.MM.Store | 79145149 54.60% 54.60% | 65821135 45.40% 100.00%
+system.ruby.L1Cache_Controller.MM.Store::total 144966284
+system.ruby.L1Cache_Controller.MM.L1_Replacement | 3416036 57.68% 57.68% | 2506720 42.32% 100.00%
+system.ruby.L1Cache_Controller.MM.L1_Replacement::total 5922756
+system.ruby.L1Cache_Controller.MM.Fwd_GETX | 37950 57.34% 57.34% | 28233 42.66% 100.00%
+system.ruby.L1Cache_Controller.MM.Fwd_GETX::total 66183
+system.ruby.L1Cache_Controller.MM.Fwd_GETS | 79392 52.90% 52.90% | 70698 47.10% 100.00%
+system.ruby.L1Cache_Controller.MM.Fwd_GETS::total 150090
+system.ruby.L1Cache_Controller.MM.Fwd_DMA | 569 57.19% 57.19% | 426 42.81% 100.00%
+system.ruby.L1Cache_Controller.MM.Fwd_DMA::total 995
+system.ruby.L1Cache_Controller.MM_W.Load | 266298 55.41% 55.41% | 214299 44.59% 100.00%
+system.ruby.L1Cache_Controller.MM_W.Load::total 480597
+system.ruby.L1Cache_Controller.MM_W.Store | 6582446 54.75% 54.75% | 5439354 45.25% 100.00%
+system.ruby.L1Cache_Controller.MM_W.Store::total 12021800
+system.ruby.L1Cache_Controller.MM_W.L1_Replacement | 3 75.00% 75.00% | 1 25.00% 100.00%
+system.ruby.L1Cache_Controller.MM_W.L1_Replacement::total 4
+system.ruby.L1Cache_Controller.MM_W.Fwd_GETX | 798 48.07% 48.07% | 862 51.93% 100.00%
+system.ruby.L1Cache_Controller.MM_W.Fwd_GETX::total 1660
+system.ruby.L1Cache_Controller.MM_W.Fwd_GETS | 405 54.22% 54.22% | 342 45.78% 100.00%
+system.ruby.L1Cache_Controller.MM_W.Fwd_GETS::total 747
+system.ruby.L1Cache_Controller.MM_W.Use_Timeout | 2872749 58.42% 58.42% | 2044770 41.58% 100.00%
+system.ruby.L1Cache_Controller.MM_W.Use_Timeout::total 4917519
+system.ruby.L1Cache_Controller.IM.Ack | 32733 43.61% 43.61% | 42322 56.39% 100.00%
+system.ruby.L1Cache_Controller.IM.Ack::total 75055
+system.ruby.L1Cache_Controller.IM.Exclusive_Data | 2275469 59.45% 59.45% | 1551882 40.55% 100.00%
+system.ruby.L1Cache_Controller.IM.Exclusive_Data::total 3827351
+system.ruby.L1Cache_Controller.SM.Fwd_GETS | 0 0.00% 0.00% | 1 100.00% 100.00%
+system.ruby.L1Cache_Controller.SM.Fwd_GETS::total 1
+system.ruby.L1Cache_Controller.SM.Inv | 4 66.67% 66.67% | 2 33.33% 100.00%
+system.ruby.L1Cache_Controller.SM.Inv::total 6
+system.ruby.L1Cache_Controller.SM.Ack | 17428 55.99% 55.99% | 13698 44.01% 100.00%
+system.ruby.L1Cache_Controller.SM.Ack::total 31126
+system.ruby.L1Cache_Controller.SM.Exclusive_Data | 118106 60.36% 60.36% | 77570 39.64% 100.00%
+system.ruby.L1Cache_Controller.SM.Exclusive_Data::total 195676
+system.ruby.L1Cache_Controller.OM.Own_GETX | 1536 50.23% 50.23% | 1522 49.77% 100.00%
+system.ruby.L1Cache_Controller.OM.Own_GETX::total 3058
+system.ruby.L1Cache_Controller.OM.Fwd_GETX | 1 16.67% 16.67% | 5 83.33% 100.00%
+system.ruby.L1Cache_Controller.OM.Fwd_GETX::total 6
+system.ruby.L1Cache_Controller.OM.Ack | 4344 51.18% 51.18% | 4144 48.82% 100.00%
+system.ruby.L1Cache_Controller.OM.Ack::total 8488
+system.ruby.L1Cache_Controller.OM.All_acks | 2395111 59.49% 59.49% | 1630974 40.51% 100.00%
+system.ruby.L1Cache_Controller.OM.All_acks::total 4026085
+system.ruby.L1Cache_Controller.IS.Data | 6875924 52.70% 52.70% | 6170294 47.30% 100.00%
+system.ruby.L1Cache_Controller.IS.Data::total 13046218
+system.ruby.L1Cache_Controller.IS.Exclusive_Data | 2504552 55.50% 55.50% | 2008104 44.50% 100.00%
+system.ruby.L1Cache_Controller.IS.Exclusive_Data::total 4512656
+system.ruby.L1Cache_Controller.SI.Load | 4145 77.19% 77.19% | 1225 22.81% 100.00%
+system.ruby.L1Cache_Controller.SI.Load::total 5370
+system.ruby.L1Cache_Controller.SI.Ifetch | 5709 81.23% 81.23% | 1319 18.77% 100.00%
+system.ruby.L1Cache_Controller.SI.Ifetch::total 7028
+system.ruby.L1Cache_Controller.SI.Store | 10 100.00% 100.00% | 0 0.00% 100.00%
+system.ruby.L1Cache_Controller.SI.Store::total 10
+system.ruby.L1Cache_Controller.SI.Fwd_GETS | 0 0.00% 0.00% | 1 100.00% 100.00%
+system.ruby.L1Cache_Controller.SI.Fwd_GETS::total 1
+system.ruby.L1Cache_Controller.SI.Writeback_Ack | 6574964 52.61% 52.61% | 5923695 47.39% 100.00%
+system.ruby.L1Cache_Controller.SI.Writeback_Ack::total 12498659
+system.ruby.L1Cache_Controller.SI.Writeback_Ack_Data | 179639 52.03% 52.03% | 165634 47.97% 100.00%
+system.ruby.L1Cache_Controller.SI.Writeback_Ack_Data::total 345273
+system.ruby.L1Cache_Controller.OI.Fwd_GETX | 2 66.67% 66.67% | 1 33.33% 100.00%
+system.ruby.L1Cache_Controller.OI.Fwd_GETX::total 3
+system.ruby.L1Cache_Controller.OI.Writeback_Ack_Data | 27973 46.61% 46.61% | 32037 53.39% 100.00%
+system.ruby.L1Cache_Controller.OI.Writeback_Ack_Data::total 60010
+system.ruby.L1Cache_Controller.MI.Load | 354 52.52% 52.52% | 320 47.48% 100.00%
+system.ruby.L1Cache_Controller.MI.Load::total 674
+system.ruby.L1Cache_Controller.MI.Ifetch | 4 100.00% 100.00% | 0 0.00% 100.00%
+system.ruby.L1Cache_Controller.MI.Ifetch::total 4
+system.ruby.L1Cache_Controller.MI.Store | 2 100.00% 100.00% | 0 0.00% 100.00%
+system.ruby.L1Cache_Controller.MI.Store::total 2
+system.ruby.L1Cache_Controller.MI.Fwd_GETX | 8 80.00% 80.00% | 2 20.00% 100.00%
+system.ruby.L1Cache_Controller.MI.Fwd_GETX::total 10
+system.ruby.L1Cache_Controller.MI.Fwd_GETS | 10 66.67% 66.67% | 5 33.33% 100.00%
+system.ruby.L1Cache_Controller.MI.Fwd_GETS::total 15
+system.ruby.L1Cache_Controller.MI.Writeback_Ack_Data | 4734283 57.61% 57.61% | 3484107 42.39% 100.00%
+system.ruby.L1Cache_Controller.MI.Writeback_Ack_Data::total 8218390
+system.ruby.L1Cache_Controller.II.Writeback_Ack_Data | 8 80.00% 80.00% | 2 20.00% 100.00%
+system.ruby.L1Cache_Controller.II.Writeback_Ack_Data::total 10
+system.ruby.L1Cache_Controller.II.Writeback_Nack | 2 66.67% 66.67% | 1 33.33% 100.00%
+system.ruby.L1Cache_Controller.II.Writeback_Nack::total 3
+system.ruby.L2Cache_Controller.L1_GETS 17569650 0.00% 0.00%
+system.ruby.L2Cache_Controller.L1_GETX 4026941 0.00% 0.00%
+system.ruby.L2Cache_Controller.L1_PUTO 60018 0.00% 0.00%
+system.ruby.L2Cache_Controller.L1_PUTX 8218470 0.00% 0.00%
+system.ruby.L2Cache_Controller.L1_PUTS_only 10753831 0.00% 0.00%
+system.ruby.L2Cache_Controller.L1_PUTS 2091031 0.00% 0.00%
+system.ruby.L2Cache_Controller.Fwd_GETX 26886 0.00% 0.00%
+system.ruby.L2Cache_Controller.Fwd_DMA 2236 0.00% 0.00%
+system.ruby.L2Cache_Controller.Inv 413 0.00% 0.00%
+system.ruby.L2Cache_Controller.IntAck 4 0.00% 0.00%
+system.ruby.L2Cache_Controller.All_Acks 1376990 0.00% 0.00%
+system.ruby.L2Cache_Controller.Data 1850112 0.00% 0.00%
+system.ruby.L2Cache_Controller.Data_Exclusive 143 0.00% 0.00%
+system.ruby.L2Cache_Controller.L1_WBCLEANDATA 345273 0.00% 0.00%
+system.ruby.L2Cache_Controller.L1_WBDIRTYDATA 8278399 0.00% 0.00%
+system.ruby.L2Cache_Controller.Writeback_Ack 1315534 0.00% 0.00%
+system.ruby.L2Cache_Controller.Unblock 25544886 0.00% 0.00%
+system.ruby.L2Cache_Controller.Exclusive_Unblock 8538741 0.00% 0.00%
+system.ruby.L2Cache_Controller.DmaAck 995 0.00% 0.00%
+system.ruby.L2Cache_Controller.L2_Replacement 1573415 0.00% 0.00%
+system.ruby.L2Cache_Controller.NP.L1_GETS 473076 0.00% 0.00%
+system.ruby.L2Cache_Controller.NP.L1_GETX 1188736 0.00% 0.00%
+system.ruby.L2Cache_Controller.NP.Inv 223 0.00% 0.00%
+system.ruby.L2Cache_Controller.I.L1_GETS 50 0.00% 0.00%
+system.ruby.L2Cache_Controller.ILS.L1_GETS 5300 0.00% 0.00%
+system.ruby.L2Cache_Controller.ILS.L1_GETX 129088 0.00% 0.00%
+system.ruby.L2Cache_Controller.ILS.L1_PUTS_only 340565 0.00% 0.00%
+system.ruby.L2Cache_Controller.ILS.L1_PUTS 4708 0.00% 0.00%
+system.ruby.L2Cache_Controller.ILS.Inv 4 0.00% 0.00%
+system.ruby.L2Cache_Controller.ILX.L1_GETS 245656 0.00% 0.00%
+system.ruby.L2Cache_Controller.ILX.L1_GETX 73690 0.00% 0.00%
+system.ruby.L2Cache_Controller.ILX.L1_PUTO 3 0.00% 0.00%
+system.ruby.L2Cache_Controller.ILX.L1_PUTX 8218400 0.00% 0.00%
+system.ruby.L2Cache_Controller.ILX.Fwd_GETX 143 0.00% 0.00%
+system.ruby.L2Cache_Controller.ILX.Fwd_DMA 995 0.00% 0.00%
+system.ruby.L2Cache_Controller.ILOX.L1_GETS 45126 0.00% 0.00%
+system.ruby.L2Cache_Controller.ILOX.L1_GETX 1850 0.00% 0.00%
+system.ruby.L2Cache_Controller.ILOX.L1_PUTO 23044 0.00% 0.00%
+system.ruby.L2Cache_Controller.ILOSX.L1_GETX 33699 0.00% 0.00%
+system.ruby.L2Cache_Controller.ILOSX.L1_PUTO 36951 0.00% 0.00%
+system.ruby.L2Cache_Controller.ILOSX.L1_PUTX 15 0.00% 0.00%
+system.ruby.L2Cache_Controller.ILOSX.L1_PUTS_only 70024 0.00% 0.00%
+system.ruby.L2Cache_Controller.S.L1_GETS 10339310 0.00% 0.00%
+system.ruby.L2Cache_Controller.S.L1_GETX 29587 0.00% 0.00%
+system.ruby.L2Cache_Controller.S.Inv 186 0.00% 0.00%
+system.ruby.L2Cache_Controller.S.L2_Replacement 256661 0.00% 0.00%
+system.ruby.L2Cache_Controller.OLSX.L1_GETS 38787 0.00% 0.00%
+system.ruby.L2Cache_Controller.OLSX.L1_GETX 6233 0.00% 0.00%
+system.ruby.L2Cache_Controller.OLSX.L1_PUTS_only 30689 0.00% 0.00%
+system.ruby.L2Cache_Controller.OLSX.L1_PUTS 37098 0.00% 0.00%
+system.ruby.L2Cache_Controller.OLSX.L2_Replacement 39 0.00% 0.00%
+system.ruby.L2Cache_Controller.SLS.L1_GETS 2049003 0.00% 0.00%
+system.ruby.L2Cache_Controller.SLS.L1_GETX 29575 0.00% 0.00%
+system.ruby.L2Cache_Controller.SLS.L1_PUTS_only 10312172 0.00% 0.00%
+system.ruby.L2Cache_Controller.SLS.L1_PUTS 2048676 0.00% 0.00%
+system.ruby.L2Cache_Controller.SLS.L2_Replacement 1220 0.00% 0.00%
+system.ruby.L2Cache_Controller.M.L1_GETS 4362566 0.00% 0.00%
+system.ruby.L2Cache_Controller.M.L1_GETX 2533627 0.00% 0.00%
+system.ruby.L2Cache_Controller.M.Fwd_GETX 26743 0.00% 0.00%
+system.ruby.L2Cache_Controller.M.Fwd_DMA 1241 0.00% 0.00%
+system.ruby.L2Cache_Controller.M.L2_Replacement 1315495 0.00% 0.00%
+system.ruby.L2Cache_Controller.IFGX.Data_Exclusive 143 0.00% 0.00%
+system.ruby.L2Cache_Controller.ILOXW.L1_GETS 1 0.00% 0.00%
+system.ruby.L2Cache_Controller.ILOXW.L1_PUTO 7 0.00% 0.00%
+system.ruby.L2Cache_Controller.ILOXW.L1_WBDIRTYDATA 23044 0.00% 0.00%
+system.ruby.L2Cache_Controller.ILOXW.Unblock 70024 0.00% 0.00%
+system.ruby.L2Cache_Controller.ILOSXW.L1_GETX 10 0.00% 0.00%
+system.ruby.L2Cache_Controller.ILOSXW.L1_PUTS_only 3 0.00% 0.00%
+system.ruby.L2Cache_Controller.ILOSXW.L1_WBDIRTYDATA 36966 0.00% 0.00%
+system.ruby.L2Cache_Controller.SLSW.L1_PUTS 548 0.00% 0.00%
+system.ruby.L2Cache_Controller.SLSW.Unblock 2048676 0.00% 0.00%
+system.ruby.L2Cache_Controller.ILSW.L1_WBCLEANDATA 4708 0.00% 0.00%
+system.ruby.L2Cache_Controller.IW.L1_WBCLEANDATA 340565 0.00% 0.00%
+system.ruby.L2Cache_Controller.SW.L1_GETS 512 0.00% 0.00%
+system.ruby.L2Cache_Controller.SW.Unblock 10312172 0.00% 0.00%
+system.ruby.L2Cache_Controller.OXW.L1_GETS 3 0.00% 0.00%
+system.ruby.L2Cache_Controller.OXW.Unblock 30689 0.00% 0.00%
+system.ruby.L2Cache_Controller.OLSXW.L1_GETX 2 0.00% 0.00%
+system.ruby.L2Cache_Controller.OLSXW.L1_PUTS 1 0.00% 0.00%
+system.ruby.L2Cache_Controller.OLSXW.Unblock 37098 0.00% 0.00%
+system.ruby.L2Cache_Controller.ILXW.L1_GETS 31 0.00% 0.00%
+system.ruby.L2Cache_Controller.ILXW.L1_GETX 12 0.00% 0.00%
+system.ruby.L2Cache_Controller.ILXW.L1_WBDIRTYDATA 8218389 0.00% 0.00%
+system.ruby.L2Cache_Controller.ILXW.Unblock 10 0.00% 0.00%
+system.ruby.L2Cache_Controller.IFLS.L1_GETX 2 0.00% 0.00%
+system.ruby.L2Cache_Controller.IFLS.L1_PUTS_only 2 0.00% 0.00%
+system.ruby.L2Cache_Controller.IFLS.Unblock 5300 0.00% 0.00%
+system.ruby.L2Cache_Controller.IFLOX.L1_GETS 1 0.00% 0.00%
+system.ruby.L2Cache_Controller.IFLOX.Unblock 45126 0.00% 0.00%
+system.ruby.L2Cache_Controller.IFLOX.Exclusive_Unblock 6233 0.00% 0.00%
+system.ruby.L2Cache_Controller.IFLOXX.L1_GETS 161 0.00% 0.00%
+system.ruby.L2Cache_Controller.IFLOXX.L1_GETX 768 0.00% 0.00%
+system.ruby.L2Cache_Controller.IFLOXX.L1_PUTO 5 0.00% 0.00%
+system.ruby.L2Cache_Controller.IFLOXX.L1_PUTX 55 0.00% 0.00%
+system.ruby.L2Cache_Controller.IFLOXX.Unblock 95566 0.00% 0.00%
+system.ruby.L2Cache_Controller.IFLOXX.Exclusive_Unblock 225630 0.00% 0.00%
+system.ruby.L2Cache_Controller.IFLXO.L1_GETS 43 0.00% 0.00%
+system.ruby.L2Cache_Controller.IFLXO.L1_GETX 31 0.00% 0.00%
+system.ruby.L2Cache_Controller.IFLXO.L1_PUTO 8 0.00% 0.00%
+system.ruby.L2Cache_Controller.IFLXO.Exclusive_Unblock 33699 0.00% 0.00%
+system.ruby.L2Cache_Controller.IGS.L1_GETS 9653 0.00% 0.00%
+system.ruby.L2Cache_Controller.IGS.Data 473126 0.00% 0.00%
+system.ruby.L2Cache_Controller.IGS.Unblock 473125 0.00% 0.00%
+system.ruby.L2Cache_Controller.IGM.Data 1218323 0.00% 0.00%
+system.ruby.L2Cache_Controller.IGMLS.L1_GETX 24 0.00% 0.00%
+system.ruby.L2Cache_Controller.IGMLS.Data 158663 0.00% 0.00%
+system.ruby.L2Cache_Controller.IGMO.L1_GETX 6 0.00% 0.00%
+system.ruby.L2Cache_Controller.IGMO.All_Acks 1376986 0.00% 0.00%
+system.ruby.L2Cache_Controller.IGMO.Exclusive_Unblock 1376986 0.00% 0.00%
+system.ruby.L2Cache_Controller.II.IntAck 4 0.00% 0.00%
+system.ruby.L2Cache_Controller.II.All_Acks 4 0.00% 0.00%
+system.ruby.L2Cache_Controller.MM.L1_GETX 1 0.00% 0.00%
+system.ruby.L2Cache_Controller.MM.Exclusive_Unblock 2533627 0.00% 0.00%
+system.ruby.L2Cache_Controller.SS.L1_GETS 364 0.00% 0.00%
+system.ruby.L2Cache_Controller.SS.Unblock 10339310 0.00% 0.00%
+system.ruby.L2Cache_Controller.OO.L1_GETS 7 0.00% 0.00%
+system.ruby.L2Cache_Controller.OO.Exclusive_Unblock 4362566 0.00% 0.00%
+system.ruby.L2Cache_Controller.OLSXS.L1_PUTS_only 4 0.00% 0.00%
+system.ruby.L2Cache_Controller.OLSXS.Unblock 38787 0.00% 0.00%
+system.ruby.L2Cache_Controller.SLSS.L1_PUTS_only 372 0.00% 0.00%
+system.ruby.L2Cache_Controller.SLSS.Unblock 2049003 0.00% 0.00%
+system.ruby.L2Cache_Controller.MI.Writeback_Ack 1315495 0.00% 0.00%
+system.ruby.L2Cache_Controller.OLSI.Writeback_Ack 39 0.00% 0.00%
+system.ruby.L2Cache_Controller.ILXD.DmaAck 995 0.00% 0.00%
+
+---------- End Simulation Statistics ----------
--- /dev/null
+
+---------- Begin Simulation Statistics ----------
+sim_seconds 51.787462
+sim_ticks 51787462200000
+final_tick 51787462200000
+sim_freq 1000000000000
+host_inst_rate 182261
+host_op_rate 216980
+host_tick_rate 11279646930
+host_mem_usage 1341804
+host_seconds 4591.23
+sim_insts 836801197
+sim_ops 996203379
+system.voltage_domain.voltage 1
+system.clk_domain.clock 1000
+system.mem_ctrls0.pwrStateResidencyTicks::UNDEFINED 51787462200000
+system.mem_ctrls0.bytes_read::ruby.dir_cntrl0 54732480
+system.mem_ctrls0.bytes_read::total 54732480
+system.mem_ctrls0.bytes_written::ruby.dir_cntrl0 42463040
+system.mem_ctrls0.bytes_written::total 42463040
+system.mem_ctrls0.num_reads::ruby.dir_cntrl0 855195
+system.mem_ctrls0.num_reads::total 855195
+system.mem_ctrls0.num_writes::ruby.dir_cntrl0 663485
+system.mem_ctrls0.num_writes::total 663485
+system.mem_ctrls0.bw_read::ruby.dir_cntrl0 1056867
+system.mem_ctrls0.bw_read::total 1056867
+system.mem_ctrls0.bw_write::ruby.dir_cntrl0 819948
+system.mem_ctrls0.bw_write::total 819948
+system.mem_ctrls0.bw_total::ruby.dir_cntrl0 1876816
+system.mem_ctrls0.bw_total::total 1876816
+system.mem_ctrls0.readReqs 855195
+system.mem_ctrls0.writeReqs 663485
+system.mem_ctrls0.readBursts 855195
+system.mem_ctrls0.writeBursts 663485
+system.mem_ctrls0.bytesReadDRAM 54638080
+system.mem_ctrls0.bytesReadWrQ 94400
+system.mem_ctrls0.bytesWritten 42460672
+system.mem_ctrls0.bytesReadSys 54732480
+system.mem_ctrls0.bytesWrittenSys 42463040
+system.mem_ctrls0.servicedByWrQ 1475
+system.mem_ctrls0.mergedWrBursts 7
+system.mem_ctrls0.neitherReadNorWriteReqs 0
+system.mem_ctrls0.perBankRdBursts::0 53979
+system.mem_ctrls0.perBankRdBursts::1 56453
+system.mem_ctrls0.perBankRdBursts::2 56859
+system.mem_ctrls0.perBankRdBursts::3 55806
+system.mem_ctrls0.perBankRdBursts::4 52130
+system.mem_ctrls0.perBankRdBursts::5 56684
+system.mem_ctrls0.perBankRdBursts::6 52943
+system.mem_ctrls0.perBankRdBursts::7 51954
+system.mem_ctrls0.perBankRdBursts::8 54653
+system.mem_ctrls0.perBankRdBursts::9 54363
+system.mem_ctrls0.perBankRdBursts::10 53142
+system.mem_ctrls0.perBankRdBursts::11 51431
+system.mem_ctrls0.perBankRdBursts::12 53363
+system.mem_ctrls0.perBankRdBursts::13 52122
+system.mem_ctrls0.perBankRdBursts::14 48274
+system.mem_ctrls0.perBankRdBursts::15 49564
+system.mem_ctrls0.perBankWrBursts::0 42330
+system.mem_ctrls0.perBankWrBursts::1 43715
+system.mem_ctrls0.perBankWrBursts::2 43620
+system.mem_ctrls0.perBankWrBursts::3 43275
+system.mem_ctrls0.perBankWrBursts::4 40870
+system.mem_ctrls0.perBankWrBursts::5 42357
+system.mem_ctrls0.perBankWrBursts::6 40606
+system.mem_ctrls0.perBankWrBursts::7 40498
+system.mem_ctrls0.perBankWrBursts::8 40878
+system.mem_ctrls0.perBankWrBursts::9 41982
+system.mem_ctrls0.perBankWrBursts::10 41541
+system.mem_ctrls0.perBankWrBursts::11 40396
+system.mem_ctrls0.perBankWrBursts::12 41596
+system.mem_ctrls0.perBankWrBursts::13 41135
+system.mem_ctrls0.perBankWrBursts::14 39231
+system.mem_ctrls0.perBankWrBursts::15 39418
+system.mem_ctrls0.numRdRetry 0
+system.mem_ctrls0.numWrRetry 0
+system.mem_ctrls0.totGap 51787460665000
+system.mem_ctrls0.readPktSize::0 0
+system.mem_ctrls0.readPktSize::1 0
+system.mem_ctrls0.readPktSize::2 0
+system.mem_ctrls0.readPktSize::3 0
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+system.mem_ctrls0.writePktSize::0 0
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+system.mem_ctrls0.writePktSize::2 0
+system.mem_ctrls0.writePktSize::3 0
+system.mem_ctrls0.writePktSize::4 0
+system.mem_ctrls0.writePktSize::5 0
+system.mem_ctrls0.writePktSize::6 663485
+system.mem_ctrls0.rdQLenPdf::0 853574
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+system.mem_ctrls0.rdQLenPdf::2 0
+system.mem_ctrls0.rdQLenPdf::3 0
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+system.mem_ctrls0.rdQLenPdf::6 0
+system.mem_ctrls0.rdQLenPdf::7 0
+system.mem_ctrls0.rdQLenPdf::8 0
+system.mem_ctrls0.rdQLenPdf::9 0
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+system.mem_ctrls0.rdQLenPdf::13 0
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+system.mem_ctrls0.rdQLenPdf::16 0
+system.mem_ctrls0.rdQLenPdf::17 0
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+system.mem_ctrls0.rdQLenPdf::23 0
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+system.mem_ctrls0.rdQLenPdf::28 0
+system.mem_ctrls0.rdQLenPdf::29 0
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+system.mem_ctrls0.rdQLenPdf::31 0
+system.mem_ctrls0.wrQLenPdf::0 1
+system.mem_ctrls0.wrQLenPdf::1 1
+system.mem_ctrls0.wrQLenPdf::2 1
+system.mem_ctrls0.wrQLenPdf::3 1
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+system.mem_ctrls0.wrQLenPdf::6 1
+system.mem_ctrls0.wrQLenPdf::7 1
+system.mem_ctrls0.wrQLenPdf::8 1
+system.mem_ctrls0.wrQLenPdf::9 1
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+system.mem_ctrls0.wrQLenPdf::13 1
+system.mem_ctrls0.wrQLenPdf::14 1
+system.mem_ctrls0.wrQLenPdf::15 29248
+system.mem_ctrls0.wrQLenPdf::16 31010
+system.mem_ctrls0.wrQLenPdf::17 35107
+system.mem_ctrls0.wrQLenPdf::18 37417
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+system.mem_ctrls0.wrQLenPdf::20 37603
+system.mem_ctrls0.wrQLenPdf::21 38022
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+system.mem_ctrls0.wrQLenPdf::23 37911
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+system.mem_ctrls0.wrQLenPdf::25 37355
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+system.mem_ctrls0.wrQLenPdf::28 37665
+system.mem_ctrls0.wrQLenPdf::29 37325
+system.mem_ctrls0.wrQLenPdf::30 37104
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+system.mem_ctrls0.wrQLenPdf::32 36808
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+system.mem_ctrls0.wrQLenPdf::34 723
+system.mem_ctrls0.wrQLenPdf::35 488
+system.mem_ctrls0.wrQLenPdf::36 418
+system.mem_ctrls0.wrQLenPdf::37 358
+system.mem_ctrls0.wrQLenPdf::38 360
+system.mem_ctrls0.wrQLenPdf::39 343
+system.mem_ctrls0.wrQLenPdf::40 325
+system.mem_ctrls0.wrQLenPdf::41 298
+system.mem_ctrls0.wrQLenPdf::42 281
+system.mem_ctrls0.wrQLenPdf::43 304
+system.mem_ctrls0.wrQLenPdf::44 216
+system.mem_ctrls0.wrQLenPdf::45 197
+system.mem_ctrls0.wrQLenPdf::46 179
+system.mem_ctrls0.wrQLenPdf::47 171
+system.mem_ctrls0.wrQLenPdf::48 150
+system.mem_ctrls0.wrQLenPdf::49 102
+system.mem_ctrls0.wrQLenPdf::50 80
+system.mem_ctrls0.wrQLenPdf::51 5
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+system.mem_ctrls0.wrQLenPdf::53 0
+system.mem_ctrls0.wrQLenPdf::54 0
+system.mem_ctrls0.wrQLenPdf::55 0
+system.mem_ctrls0.wrQLenPdf::56 0
+system.mem_ctrls0.wrQLenPdf::57 0
+system.mem_ctrls0.wrQLenPdf::58 0
+system.mem_ctrls0.wrQLenPdf::59 0
+system.mem_ctrls0.wrQLenPdf::60 0
+system.mem_ctrls0.wrQLenPdf::61 0
+system.mem_ctrls0.wrQLenPdf::62 0
+system.mem_ctrls0.wrQLenPdf::63 0
+system.mem_ctrls0.bytesPerActivate::samples 464954
+system.mem_ctrls0.bytesPerActivate::mean 208.834766
+system.mem_ctrls0.bytesPerActivate::gmean 125.209988
+system.mem_ctrls0.bytesPerActivate::stdev 270.988110
+system.mem_ctrls0.bytesPerActivate::0-127 249011 53.56% 53.56%
+system.mem_ctrls0.bytesPerActivate::128-255 113120 24.33% 77.89%
+system.mem_ctrls0.bytesPerActivate::256-383 31905 6.86% 84.75%
+system.mem_ctrls0.bytesPerActivate::384-511 15844 3.41% 88.15%
+system.mem_ctrls0.bytesPerActivate::512-639 8162 1.76% 89.91%
+system.mem_ctrls0.bytesPerActivate::640-767 5473 1.18% 91.09%
+system.mem_ctrls0.bytesPerActivate::768-895 4605 0.99% 92.08%
+system.mem_ctrls0.bytesPerActivate::896-1023 4316 0.93% 93.01%
+system.mem_ctrls0.bytesPerActivate::1024-1151 32518 6.99% 100.00%
+system.mem_ctrls0.bytesPerActivate::total 464954
+system.mem_ctrls0.rdPerTurnAround::samples 36564
+system.mem_ctrls0.rdPerTurnAround::mean 23.347911
+system.mem_ctrls0.rdPerTurnAround::stdev 151.279974
+system.mem_ctrls0.rdPerTurnAround::0-1023 36561 99.99% 99.99%
+system.mem_ctrls0.rdPerTurnAround::1024-2047 2 0.01% 100.00%
+system.mem_ctrls0.rdPerTurnAround::27648-28671 1 0.00% 100.00%
+system.mem_ctrls0.rdPerTurnAround::total 36564
+system.mem_ctrls0.wrPerTurnAround::samples 36564
+system.mem_ctrls0.wrPerTurnAround::mean 18.144842
+system.mem_ctrls0.wrPerTurnAround::gmean 18.046618
+system.mem_ctrls0.wrPerTurnAround::stdev 2.223089
+system.mem_ctrls0.wrPerTurnAround::16 6078 16.62% 16.62%
+system.mem_ctrls0.wrPerTurnAround::17 812 2.22% 18.84%
+system.mem_ctrls0.wrPerTurnAround::18 23208 63.47% 82.32%
+system.mem_ctrls0.wrPerTurnAround::19 3494 9.56% 91.87%
+system.mem_ctrls0.wrPerTurnAround::20 1174 3.21% 95.08%
+system.mem_ctrls0.wrPerTurnAround::21 422 1.15% 96.24%
+system.mem_ctrls0.wrPerTurnAround::22 634 1.73% 97.97%
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+system.ruby.Load_Linked.miss_latency_hist_seqr | 253304 99.43% 99.43% | 314 0.12% 99.56% | 290 0.11% 99.67% | 15 0.01% 99.68% | 809 0.32% 100.00% | 10 0.00% 100.00% | 2 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00%
+system.ruby.Load_Linked.miss_latency_hist_seqr::total 254744
+system.ruby.Store_Conditional.latency_hist_seqr::bucket_size 1
+system.ruby.Store_Conditional.latency_hist_seqr::max_bucket 9
+system.ruby.Store_Conditional.latency_hist_seqr::samples 4087163
+system.ruby.Store_Conditional.latency_hist_seqr::mean 1
+system.ruby.Store_Conditional.latency_hist_seqr::gmean 1
+system.ruby.Store_Conditional.latency_hist_seqr | 0 0.00% 0.00% | 4087163 100.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00%
+system.ruby.Store_Conditional.latency_hist_seqr::total 4087163
+system.ruby.Store_Conditional.hit_latency_hist_seqr::bucket_size 1
+system.ruby.Store_Conditional.hit_latency_hist_seqr::max_bucket 9
+system.ruby.Store_Conditional.hit_latency_hist_seqr::samples 4087163
+system.ruby.Store_Conditional.hit_latency_hist_seqr::mean 1
+system.ruby.Store_Conditional.hit_latency_hist_seqr::gmean 1
+system.ruby.Store_Conditional.hit_latency_hist_seqr | 0 0.00% 0.00% | 4087163 100.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00%
+system.ruby.Store_Conditional.hit_latency_hist_seqr::total 4087163
+system.ruby.Directory_Controller.GETX | 642301 50.16% 50.16% | 638171 49.84% 100.00%
+system.ruby.Directory_Controller.GETX::total 1280472
+system.ruby.Directory_Controller.GETS | 209940 51.43% 51.43% | 198235 48.57% 100.00%
+system.ruby.Directory_Controller.GETS::total 408175
+system.ruby.Directory_Controller.PUTX | 610150 50.18% 50.18% | 605771 49.82% 100.00%
+system.ruby.Directory_Controller.PUTX::total 1215921
+system.ruby.Directory_Controller.Unblock | 136462 51.56% 51.56% | 128179 48.44% 100.00%
+system.ruby.Directory_Controller.Unblock::total 264641
+system.ruby.Directory_Controller.Last_Unblock | 73477 51.19% 51.19% | 70056 48.81% 100.00%
+system.ruby.Directory_Controller.Last_Unblock::total 143533
+system.ruby.Directory_Controller.Exclusive_Unblock | 695636 50.15% 50.15% | 691503 49.85% 100.00%
+system.ruby.Directory_Controller.Exclusive_Unblock::total 1387139
+system.ruby.Directory_Controller.Dirty_Writeback | 610150 50.18% 50.18% | 605771 49.82% 100.00%
+system.ruby.Directory_Controller.Dirty_Writeback::total 1215921
+system.ruby.Directory_Controller.Memory_Data | 855195 50.47% 50.47% | 839384 49.53% 100.00%
+system.ruby.Directory_Controller.Memory_Data::total 1694579
+system.ruby.Directory_Controller.Memory_Ack | 663485 50.17% 50.17% | 659103 49.83% 100.00%
+system.ruby.Directory_Controller.Memory_Ack::total 1322588
+system.ruby.Directory_Controller.DMA_READ | 4897 54.82% 54.82% | 4036 45.18% 100.00%
+system.ruby.Directory_Controller.DMA_READ::total 8933
+system.ruby.Directory_Controller.DMA_WRITE | 53335 50.00% 50.00% | 53332 50.00% 100.00%
+system.ruby.Directory_Controller.DMA_WRITE::total 106667
+system.ruby.Directory_Controller.DMA_ACK | 1742 67.18% 67.18% | 851 32.82% 100.00%
+system.ruby.Directory_Controller.DMA_ACK::total 2593
+system.ruby.Directory_Controller.Data | 15370 49.84% 49.84% | 15466 50.16% 100.00%
+system.ruby.Directory_Controller.Data::total 30836
+system.ruby.Directory_Controller.I.GETX | 550649 49.84% 49.84% | 554206 50.16% 100.00%
+system.ruby.Directory_Controller.I.GETX::total 1104855
+system.ruby.Directory_Controller.I.GETS | 136463 51.57% 51.57% | 128179 48.43% 100.00%
+system.ruby.Directory_Controller.I.GETS::total 264642
+system.ruby.Directory_Controller.I.Memory_Ack | 610272 50.18% 50.18% | 605875 49.82% 100.00%
+system.ruby.Directory_Controller.I.Memory_Ack::total 1216147
+system.ruby.Directory_Controller.I.DMA_READ | 2954 49.80% 49.80% | 2978 50.20% 100.00%
+system.ruby.Directory_Controller.I.DMA_READ::total 5932
+system.ruby.Directory_Controller.I.DMA_WRITE | 37712 50.06% 50.06% | 37620 49.94% 100.00%
+system.ruby.Directory_Controller.I.DMA_WRITE::total 75332
+system.ruby.Directory_Controller.S.GETX | 91652 52.19% 52.19% | 83965 47.81% 100.00%
+system.ruby.Directory_Controller.S.GETX::total 175617
+system.ruby.Directory_Controller.S.GETS | 73477 51.19% 51.19% | 70056 48.81% 100.00%
+system.ruby.Directory_Controller.S.GETS::total 143533
+system.ruby.Directory_Controller.S.DMA_READ | 201 49.26% 49.26% | 207 50.74% 100.00%
+system.ruby.Directory_Controller.S.DMA_READ::total 408
+system.ruby.Directory_Controller.S.DMA_WRITE | 253 50.70% 50.70% | 246 49.30% 100.00%
+system.ruby.Directory_Controller.S.DMA_WRITE::total 499
+system.ruby.Directory_Controller.M.PUTX | 610150 50.18% 50.18% | 605771 49.82% 100.00%
+system.ruby.Directory_Controller.M.PUTX::total 1215921
+system.ruby.Directory_Controller.M.DMA_READ | 1742 67.18% 67.18% | 851 32.82% 100.00%
+system.ruby.Directory_Controller.M.DMA_READ::total 2593
+system.ruby.Directory_Controller.M.DMA_WRITE | 15370 49.84% 49.84% | 15466 50.16% 100.00%
+system.ruby.Directory_Controller.M.DMA_WRITE::total 30836
+system.ruby.Directory_Controller.IS.Unblock | 136462 51.56% 51.56% | 128179 48.44% 100.00%
+system.ruby.Directory_Controller.IS.Unblock::total 264641
+system.ruby.Directory_Controller.IS.Memory_Data | 136463 51.57% 51.57% | 128179 48.43% 100.00%
+system.ruby.Directory_Controller.IS.Memory_Data::total 264642
+system.ruby.Directory_Controller.SS.Last_Unblock | 73477 51.19% 51.19% | 70056 48.81% 100.00%
+system.ruby.Directory_Controller.SS.Last_Unblock::total 143533
+system.ruby.Directory_Controller.SS.Memory_Data | 73477 51.19% 51.19% | 70056 48.81% 100.00%
+system.ruby.Directory_Controller.SS.Memory_Data::total 143533
+system.ruby.Directory_Controller.MM.Exclusive_Unblock | 642301 50.16% 50.16% | 638171 49.84% 100.00%
+system.ruby.Directory_Controller.MM.Exclusive_Unblock::total 1280472
+system.ruby.Directory_Controller.MM.Memory_Data | 642301 50.16% 50.16% | 638171 49.84% 100.00%
+system.ruby.Directory_Controller.MM.Memory_Data::total 1280472
+system.ruby.Directory_Controller.MM.Memory_Ack | 1 100.00% 100.00% | 0 0.00% 100.00%
+system.ruby.Directory_Controller.MM.Memory_Ack::total 1
+system.ruby.Directory_Controller.MI.Dirty_Writeback | 610150 50.18% 50.18% | 605771 49.82% 100.00%
+system.ruby.Directory_Controller.MI.Dirty_Writeback::total 1215921
+system.ruby.Directory_Controller.XI_M.Memory_Data | 2954 49.80% 49.80% | 2978 50.20% 100.00%
+system.ruby.Directory_Controller.XI_M.Memory_Data::total 5932
+system.ruby.Directory_Controller.XI_U.Exclusive_Unblock | 53335 50.00% 50.00% | 53332 50.00% 100.00%
+system.ruby.Directory_Controller.XI_U.Exclusive_Unblock::total 106667
+system.ruby.Directory_Controller.XI_U.Memory_Ack | 53212 49.99% 49.99% | 53228 50.01% 100.00%
+system.ruby.Directory_Controller.XI_U.Memory_Ack::total 106440
+system.ruby.Directory_Controller.OI_D.Data | 15370 49.84% 49.84% | 15466 50.16% 100.00%
+system.ruby.Directory_Controller.OI_D.Data::total 30836
+system.ruby.Directory_Controller.MD.DMA_ACK | 1742 67.18% 67.18% | 851 32.82% 100.00%
+system.ruby.Directory_Controller.MD.DMA_ACK::total 2593
+system.ruby.DMA_Controller.ReadRequest | 0 0.00% 0.00% | 0 0.00% 0.00% | 0 0.00% 0.00% | 249564 99.92% 99.92% | 202 0.08% 100.00% | 0 0.00% 100.00%
+system.ruby.DMA_Controller.ReadRequest::total 249766
+system.ruby.DMA_Controller.WriteRequest | 0 0.00% 0.00% | 0 0.00% 0.00% | 0 0.00% 0.00% | 3303262 100.00% 100.00% | 3 0.00% 100.00% | 0 0.00% 100.00%
+system.ruby.DMA_Controller.WriteRequest::total 3303265
+system.ruby.DMA_Controller.Data | 0 0.00% 0.00% | 0 0.00% 0.00% | 0 0.00% 0.00% | 8896 99.59% 99.59% | 37 0.41% 100.00% | 0 0.00% 100.00%
+system.ruby.DMA_Controller.Data::total 8933
+system.ruby.DMA_Controller.DMA_Ack | 0 0.00% 0.00% | 0 0.00% 0.00% | 0 0.00% 0.00% | 106664 100.00% 100.00% | 3 0.00% 100.00% | 0 0.00% 100.00%
+system.ruby.DMA_Controller.DMA_Ack::total 106667
+system.ruby.DMA_Controller.Inv_Ack | 0 0.00% 0.00% | 0 0.00% 0.00% | 0 0.00% 0.00% | 499 100.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00%
+system.ruby.DMA_Controller.Inv_Ack::total 499
+system.ruby.DMA_Controller.All_Acks | 0 0.00% 0.00% | 0 0.00% 0.00% | 0 0.00% 0.00% | 106664 100.00% 100.00% | 3 0.00% 100.00% | 0 0.00% 100.00%
+system.ruby.DMA_Controller.All_Acks::total 106667
+system.ruby.DMA_Controller.READY.ReadRequest | 0 0.00% 0.00% | 0 0.00% 0.00% | 0 0.00% 0.00% | 8896 99.59% 99.59% | 37 0.41% 100.00% | 0 0.00% 100.00%
+system.ruby.DMA_Controller.READY.ReadRequest::total 8933
+system.ruby.DMA_Controller.READY.WriteRequest | 0 0.00% 0.00% | 0 0.00% 0.00% | 0 0.00% 0.00% | 106664 100.00% 100.00% | 3 0.00% 100.00% | 0 0.00% 100.00%
+system.ruby.DMA_Controller.READY.WriteRequest::total 106667
+system.ruby.DMA_Controller.BUSY_RD.ReadRequest | 0 0.00% 0.00% | 0 0.00% 0.00% | 0 0.00% 0.00% | 240668 99.93% 99.93% | 165 0.07% 100.00% | 0 0.00% 100.00%
+system.ruby.DMA_Controller.BUSY_RD.ReadRequest::total 240833
+system.ruby.DMA_Controller.BUSY_RD.Data | 0 0.00% 0.00% | 0 0.00% 0.00% | 0 0.00% 0.00% | 8896 99.59% 99.59% | 37 0.41% 100.00% | 0 0.00% 100.00%
+system.ruby.DMA_Controller.BUSY_RD.Data::total 8933
+system.ruby.DMA_Controller.BUSY_WR.WriteRequest | 0 0.00% 0.00% | 0 0.00% 0.00% | 0 0.00% 0.00% | 3196598 100.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00%
+system.ruby.DMA_Controller.BUSY_WR.WriteRequest::total 3196598
+system.ruby.DMA_Controller.BUSY_WR.DMA_Ack | 0 0.00% 0.00% | 0 0.00% 0.00% | 0 0.00% 0.00% | 106664 100.00% 100.00% | 3 0.00% 100.00% | 0 0.00% 100.00%
+system.ruby.DMA_Controller.BUSY_WR.DMA_Ack::total 106667
+system.ruby.DMA_Controller.BUSY_WR.Inv_Ack | 0 0.00% 0.00% | 0 0.00% 0.00% | 0 0.00% 0.00% | 499 100.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00%
+system.ruby.DMA_Controller.BUSY_WR.Inv_Ack::total 499
+system.ruby.DMA_Controller.BUSY_WR.All_Acks | 0 0.00% 0.00% | 0 0.00% 0.00% | 0 0.00% 0.00% | 106664 100.00% 100.00% | 3 0.00% 100.00% | 0 0.00% 100.00%
+system.ruby.DMA_Controller.BUSY_WR.All_Acks::total 106667
+system.ruby.L1Cache_Controller.Load 167785000 0.00% 0.00%
+system.ruby.L1Cache_Controller.Ifetch 837412033 0.00% 0.00%
+system.ruby.L1Cache_Controller.Store 159465905 0.00% 0.00%
+system.ruby.L1Cache_Controller.L1_Replacement 20311774 0.00% 0.00%
+system.ruby.L1Cache_Controller.Fwd_GETX 46 0.00% 0.00%
+system.ruby.L1Cache_Controller.Fwd_DMA 899 0.00% 0.00%
+system.ruby.L1Cache_Controller.Inv 4 0.00% 0.00%
+system.ruby.L1Cache_Controller.Data 12213133 0.00% 0.00%
+system.ruby.L1Cache_Controller.Exclusive_Data 8229365 0.00% 0.00%
+system.ruby.L1Cache_Controller.Writeback_Ack 11782494 0.00% 0.00%
+system.ruby.L1Cache_Controller.Writeback_Ack_Data 8529231 0.00% 0.00%
+system.ruby.L1Cache_Controller.Writeback_Nack 1 0.00% 0.00%
+system.ruby.L1Cache_Controller.All_acks 3849849 0.00% 0.00%
+system.ruby.L1Cache_Controller.Use_Timeout 8229365 0.00% 0.00%
+system.ruby.L1Cache_Controller.I.Load 7020240 0.00% 0.00%
+system.ruby.L1Cache_Controller.I.Ifetch 9572409 0.00% 0.00%
+system.ruby.L1Cache_Controller.I.Store 3720149 0.00% 0.00%
+system.ruby.L1Cache_Controller.I.L1_Replacement 42 0.00% 0.00%
+system.ruby.L1Cache_Controller.S.Load 21110173 0.00% 0.00%
+system.ruby.L1Cache_Controller.S.Ifetch 827832452 0.00% 0.00%
+system.ruby.L1Cache_Controller.S.Store 129700 0.00% 0.00%
+system.ruby.L1Cache_Controller.S.L1_Replacement 12082835 0.00% 0.00%
+system.ruby.L1Cache_Controller.S.Inv 4 0.00% 0.00%
+system.ruby.L1Cache_Controller.M.Load 21542467 0.00% 0.00%
+system.ruby.L1Cache_Controller.M.Store 1206008 0.00% 0.00%
+system.ruby.L1Cache_Controller.M.L1_Replacement 2311586 0.00% 0.00%
+system.ruby.L1Cache_Controller.M.Fwd_GETX 1 0.00% 0.00%
+system.ruby.L1Cache_Controller.M_W.Load 1919137 0.00% 0.00%
+system.ruby.L1Cache_Controller.M_W.Store 861844 0.00% 0.00%
+system.ruby.L1Cache_Controller.M_W.L1_Replacement 6 0.00% 0.00%
+system.ruby.L1Cache_Controller.M_W.Use_Timeout 3517672 0.00% 0.00%
+system.ruby.L1Cache_Controller.MM.Load 115730356 0.00% 0.00%
+system.ruby.L1Cache_Controller.MM.Store 141996199 0.00% 0.00%
+system.ruby.L1Cache_Controller.MM.L1_Replacement 5917305 0.00% 0.00%
+system.ruby.L1Cache_Controller.MM.Fwd_GETX 44 0.00% 0.00%
+system.ruby.L1Cache_Controller.MM.Fwd_DMA 899 0.00% 0.00%
+system.ruby.L1Cache_Controller.MM_W.Load 456754 0.00% 0.00%
+system.ruby.L1Cache_Controller.MM_W.Store 11551993 0.00% 0.00%
+system.ruby.L1Cache_Controller.MM_W.Use_Timeout 4711693 0.00% 0.00%
+system.ruby.L1Cache_Controller.IM.Exclusive_Data 3720149 0.00% 0.00%
+system.ruby.L1Cache_Controller.SM.Exclusive_Data 129700 0.00% 0.00%
+system.ruby.L1Cache_Controller.OM.All_acks 3849849 0.00% 0.00%
+system.ruby.L1Cache_Controller.IS.Data 12213133 0.00% 0.00%
+system.ruby.L1Cache_Controller.IS.Exclusive_Data 4379516 0.00% 0.00%
+system.ruby.L1Cache_Controller.SI.Load 5283 0.00% 0.00%
+system.ruby.L1Cache_Controller.SI.Ifetch 7172 0.00% 0.00%
+system.ruby.L1Cache_Controller.SI.Store 10 0.00% 0.00%
+system.ruby.L1Cache_Controller.SI.Writeback_Ack 11782494 0.00% 0.00%
+system.ruby.L1Cache_Controller.SI.Writeback_Ack_Data 300341 0.00% 0.00%
+system.ruby.L1Cache_Controller.MI.Load 590 0.00% 0.00%
+system.ruby.L1Cache_Controller.MI.Store 2 0.00% 0.00%
+system.ruby.L1Cache_Controller.MI.Fwd_GETX 1 0.00% 0.00%
+system.ruby.L1Cache_Controller.MI.Writeback_Ack_Data 8228890 0.00% 0.00%
+system.ruby.L1Cache_Controller.II.Writeback_Nack 1 0.00% 0.00%
+system.ruby.L2Cache_Controller.L1_GETS 16592651 0.00% 0.00%
+system.ruby.L2Cache_Controller.L1_GETX 3849849 0.00% 0.00%
+system.ruby.L2Cache_Controller.L1_PUTX 8228892 0.00% 0.00%
+system.ruby.L2Cache_Controller.L1_PUTS_only 12082835 0.00% 0.00%
+system.ruby.L2Cache_Controller.Fwd_GETX 30836 0.00% 0.00%
+system.ruby.L2Cache_Controller.Fwd_DMA 2593 0.00% 0.00%
+system.ruby.L2Cache_Controller.Inv 499 0.00% 0.00%
+system.ruby.L2Cache_Controller.IntAck 4 0.00% 0.00%
+system.ruby.L2Cache_Controller.All_Acks 1280476 0.00% 0.00%
+system.ruby.L2Cache_Controller.Data 1688647 0.00% 0.00%
+system.ruby.L2Cache_Controller.Data_Exclusive 46 0.00% 0.00%
+system.ruby.L2Cache_Controller.L1_WBCLEANDATA 300341 0.00% 0.00%
+system.ruby.L2Cache_Controller.L1_WBDIRTYDATA 8228890 0.00% 0.00%
+system.ruby.L2Cache_Controller.Writeback_Ack 1215921 0.00% 0.00%
+system.ruby.L2Cache_Controller.Unblock 23995626 0.00% 0.00%
+system.ruby.L2Cache_Controller.Exclusive_Unblock 8229365 0.00% 0.00%
+system.ruby.L2Cache_Controller.DmaAck 899 0.00% 0.00%
+system.ruby.L2Cache_Controller.L2_Replacement 1434025 0.00% 0.00%
+system.ruby.L2Cache_Controller.NP.L1_GETS 408154 0.00% 0.00%
+system.ruby.L2Cache_Controller.NP.L1_GETX 1119537 0.00% 0.00%
+system.ruby.L2Cache_Controller.NP.Inv 368 0.00% 0.00%
+system.ruby.L2Cache_Controller.I.L1_GETS 21 0.00% 0.00%
+system.ruby.L2Cache_Controller.I.L1_PUTX 1 0.00% 0.00%
+system.ruby.L2Cache_Controller.ILS.L1_GETX 108445 0.00% 0.00%
+system.ruby.L2Cache_Controller.ILS.L1_PUTS_only 300341 0.00% 0.00%
+system.ruby.L2Cache_Controller.ILS.Inv 3 0.00% 0.00%
+system.ruby.L2Cache_Controller.ILX.L1_PUTX 8228890 0.00% 0.00%
+system.ruby.L2Cache_Controller.ILX.Fwd_GETX 46 0.00% 0.00%
+system.ruby.L2Cache_Controller.ILX.Fwd_DMA 899 0.00% 0.00%
+system.ruby.L2Cache_Controller.S.L1_GETS 11804958 0.00% 0.00%
+system.ruby.L2Cache_Controller.S.L1_GETX 31235 0.00% 0.00%
+system.ruby.L2Cache_Controller.S.Inv 127 0.00% 0.00%
+system.ruby.L2Cache_Controller.S.L2_Replacement 217484 0.00% 0.00%
+system.ruby.L2Cache_Controller.SLS.L1_GETX 21255 0.00% 0.00%
+system.ruby.L2Cache_Controller.SLS.L1_PUTS_only 11782494 0.00% 0.00%
+system.ruby.L2Cache_Controller.SLS.Inv 1 0.00% 0.00%
+system.ruby.L2Cache_Controller.SLS.L2_Replacement 620 0.00% 0.00%
+system.ruby.L2Cache_Controller.M.L1_GETS 4379516 0.00% 0.00%
+system.ruby.L2Cache_Controller.M.L1_GETX 2569377 0.00% 0.00%
+system.ruby.L2Cache_Controller.M.Fwd_GETX 30790 0.00% 0.00%
+system.ruby.L2Cache_Controller.M.Fwd_DMA 1694 0.00% 0.00%
+system.ruby.L2Cache_Controller.M.L2_Replacement 1215921 0.00% 0.00%
+system.ruby.L2Cache_Controller.IFGX.L1_PUTX 1 0.00% 0.00%
+system.ruby.L2Cache_Controller.IFGX.Data_Exclusive 46 0.00% 0.00%
+system.ruby.L2Cache_Controller.IW.L1_WBCLEANDATA 300341 0.00% 0.00%
+system.ruby.L2Cache_Controller.SW.L1_GETS 2 0.00% 0.00%
+system.ruby.L2Cache_Controller.SW.Unblock 11782494 0.00% 0.00%
+system.ruby.L2Cache_Controller.ILXW.L1_WBDIRTYDATA 8228890 0.00% 0.00%
+system.ruby.L2Cache_Controller.IGS.Data 408175 0.00% 0.00%
+system.ruby.L2Cache_Controller.IGS.Unblock 408174 0.00% 0.00%
+system.ruby.L2Cache_Controller.IGM.Data 1150772 0.00% 0.00%
+system.ruby.L2Cache_Controller.IGMLS.Data 129700 0.00% 0.00%
+system.ruby.L2Cache_Controller.IGMO.All_Acks 1280472 0.00% 0.00%
+system.ruby.L2Cache_Controller.IGMO.Exclusive_Unblock 1280472 0.00% 0.00%
+system.ruby.L2Cache_Controller.II.IntAck 4 0.00% 0.00%
+system.ruby.L2Cache_Controller.II.All_Acks 4 0.00% 0.00%
+system.ruby.L2Cache_Controller.MM.Exclusive_Unblock 2569377 0.00% 0.00%
+system.ruby.L2Cache_Controller.SS.Unblock 11804958 0.00% 0.00%
+system.ruby.L2Cache_Controller.OO.Exclusive_Unblock 4379516 0.00% 0.00%
+system.ruby.L2Cache_Controller.MI.Writeback_Ack 1215921 0.00% 0.00%
+system.ruby.L2Cache_Controller.ILXD.DmaAck 899 0.00% 0.00%
+
+---------- End Simulation Statistics ----------
projects / gem5.git / commitdiff