integration/soc: add FPGA device and System clock to logs.

diff --git a/litex/soc/integration/soc.py b/litex/soc/integration/soc.py
index 30f91f9164345f7d940b9464c92c498b5c7925ba..c8abc75af0a0ef31187fbd3254ad0f6112606ece 100644 (file)
--- a/litex/soc/integration/soc.py
+++ b/litex/soc/integration/soc.py
@@ -661,6 +661,8 @@ class SoC(Module):
         self.logger.info(colorer("-"*80, color="bright"))
         self.logger.info(colorer("Creating SoC... ({})".format(build_time())))
         self.logger.info(colorer("-"*80, color="bright"))
+        self.logger.info("FPGA device : {}.".format(platform.device))
+        self.logger.info("System clock: {:3.2f}MHz.".format(sys_clk_freq/1e6))
 
         # SoC attributes ---------------------------------------------------------------------------
         self.platform     = platform