add sv.maddld test case

diff --git a/src/openpower/decoder/isa/test_caller_mul.py b/src/openpower/decoder/isa/test_caller_mul.py
index 24b2f00de8fcae49fc2366c24e0aed990048f68f..eb1441f23d223d5344b7d55d2203a35dda6e2685 100644 (file)
--- a/src/openpower/decoder/isa/test_caller_mul.py
+++ b/src/openpower/decoder/isa/test_caller_mul.py
@@ -7,7 +7,7 @@ related bugs:
 
 import unittest
 from openpower.test.runner import TestRunnerBase
-from openpower.test.mul.mul_cases import MulTestCases2Arg
+from openpower.test.mul.mul_cases import MulTestCases2Arg, SVP64MAdd
 
 # writing the test_caller invocation this way makes it work with pytest
 
@@ -22,5 +22,15 @@ class TestMul2Arg(TestRunnerBase):
         pass
 
 
+class TestSVP64MAdd(TestRunnerBase):
+    def __init__(self, test):
+        assert test == 'test'
+        super().__init__(SVP64MAdd().test_data)
+
+    def test(self):
+        # dummy function to make unittest try to test this class
+        pass
+
+
 if __name__ == "__main__":
     unittest.main()

diff --git a/src/openpower/test/mul/mul_cases.py b/src/openpower/test/mul/mul_cases.py
index 7b751f9200708a99699eb5b9f9024a3e6c30a0e0..bd456a5a009a241d4fd1ec17759fc8c8022a9b76 100644 (file)
--- a/src/openpower/test/mul/mul_cases.py
+++ b/src/openpower/test/mul/mul_cases.py
@@ -2,7 +2,8 @@ from openpower.simulator.program import Program
 from openpower.endian import bigendian
 from openpower.test.common import TestAccumulatorBase, skip_case
 from openpower.test.state import ExpectedState
-
+from openpower.sv.trans.svp64 import SVP64Asm
+from openpower.decoder.isa.caller import SVP64State
 import random
 
 
@@ -156,3 +157,17 @@ class MulTestCases3Arg(TestAccumulatorBase):
         self.add_case(Program(lst, bigendian), initial_regs)
 
 
+class SVP64MAdd(TestAccumulatorBase):
+    # TODO add test case for these 3 operand cases (madd
+    # needs to be implemented)
+    # "maddhd","maddhdu","maddld"
+    def case_sv_maddld(self):
+        lst = list(SVP64Asm(["sv.maddld *4, *8, *12, 16"]))
+        initial_regs = [0] * 32
+        initial_regs[8:16] = range(1, 17)
+        initial_regs[16] = 0x10000
+        svstate = SVP64State()
+        svstate.vl = 4
+        svstate.maxvl = 4
+        self.add_case(Program(lst, bigendian), initial_regs,
+                      initial_svstate=svstate)