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diff --git a/openpower/sv/bitmanip/appendix.mdwn b/openpower/sv/bitmanip/appendix.mdwn
index edf85fea0f9f34acf0aa91061f009d874c0aee0e..e798949475e15d4bad453d09dbc7f4881090dc82 100644 (file)
--- a/openpower/sv/bitmanip/appendix.mdwn
+++ b/openpower/sv/bitmanip/appendix.mdwn
@@ -42,28 +42,33 @@ The key loop may be implemented with a 4-in, 2-out mul-twin-add
 ```
 On Sat, Apr 16, 2022, 22:06 Jacob Lifshay <programmerjake@gmail.com> wrote:
 and a mrsubcarry (the one actually needed by bigint division):
-# for big_c - big_a * word_b
-result <- RC + ~(RA * RB) + CARRY # this expression is wrong, needs further thought
-CARRY <- HIGH_HALF(result)
-RT <- LOW_HALF(result)
-
-turns out, after some checking with 4-bit words, afaict the correct algorithm for mrsubcarry is:
-# for big_c - big_a * word_b
-result <- RC + ~(RA * RB) + CARRY
-result_high <- HIGH_HALF(result)
-if CARRY <= 1 then # unsigned comparison
-    result_high <- result_high + 1
-end
-CARRY <- result_high
-RT <- LOW_HALF(result)
+
+    # for big_c - big_a * word_b
+    result <- RC + ~(RA * RB) + CARRY # wrong, needs further thought
+    CARRY <- HIGH_HALF(result)
+    RT <- LOW_HALF(result)
+
+turns out, after some checking with 4-bit words, afaict the correct
+algorithm for mrsubcarry is:
+
+    # for big_c - big_a * word_b
+    result <- RC + ~(RA * RB) + CARRY
+    result_high <- HIGH_HALF(result)
+    if CARRY <= 1 then # unsigned comparison
+        result_high <- result_high + 1
+    end
+    CARRY <- result_high
+    RT <- LOW_HALF(result)
 
 afaict, that'll make the following algorithm work:
 
-so the inner loop in the bigint division algorithm would end up being (assuming n, d, and q all fit in registers):
-li r3, 1 # carry in for subtraction
-mtspr CARRY, r3 # init carry spr
-setvl loop_count
-sv.mrsubcarry rn.v, rd.v, rq.s, rn.v
+so the inner loop in the bigint division algorithm would end up being
+(assuming n, d, and q all fit in registers):
+
+    li r3, 1 # carry in for subtraction
+    mtspr CARRY, r3 # init carry spr
+    setvl loop_count
+    sv.mrsubcarry rn.v, rd.v, rq.s, rn.v
 ```
 
 This algorithm may be morphed into a pair of Vector operations by temporary