litesata/example_designs: fix core generation (RAID introduced some changes on the...

diff --git a/misoclib/mem/litesata/example_designs/platforms/verilog_backend.py b/misoclib/mem/litesata/example_designs/platforms/verilog_backend.py
index 3780b2da5dd614404f68f3ad0254f6bb520043bd..095913e425a099d037a1ea1481c4b4db312360ed 100644 (file)
--- a/misoclib/mem/litesata/example_designs/platforms/verilog_backend.py
+++ b/misoclib/mem/litesata/example_designs/platforms/verilog_backend.py
@@ -4,14 +4,15 @@ from mibuild.xilinx.platform import XilinxPlatform
 _io = [
     ("sys_clk", 0, Pins("X")),
     ("sys_rst", 1, Pins("X")),
-
+    ("sata_clocks", 0,
+        Subsignal("refclk_p", Pins("X")),
+        Subsignal("refclk_n", Pins("X")),
+    ),
     ("sata", 0,
-        Subsignal("refclk_p", Pins("C8")),
-        Subsignal("refclk_n", Pins("C7")),
-        Subsignal("txp", Pins("D2")),
-        Subsignal("txn", Pins("D1")),
-        Subsignal("rxp", Pins("E4")),
-        Subsignal("rxn", Pins("E3")),
+        Subsignal("txp", Pins("X")),
+        Subsignal("txn", Pins("X")),
+        Subsignal("rxp", Pins("X")),
+        Subsignal("rxn", Pins("X")),
     ),
 ]
 

diff --git a/misoclib/mem/litesata/example_designs/targets/core.py b/misoclib/mem/litesata/example_designs/targets/core.py
index e15b259a83b33718529e3ddd58944bc7c43a9f6d..9fbdc05373fa60f7a133f7927160905179c54fd6 100644 (file)
--- a/misoclib/mem/litesata/example_designs/targets/core.py
+++ b/misoclib/mem/litesata/example_designs/targets/core.py
@@ -17,7 +17,7 @@ class Core(Module):
         self.clk_freq = clk_freq
 
         # SATA PHY/Core/Frontend
-        self.submodules.sata_phy = LiteSATAPHY(platform.device, platform.request("sys_clk"), platform.request("sata"), "sata_gen2", clk_freq)
+        self.submodules.sata_phy = LiteSATAPHY(platform.device, platform.request("sata_clocks"), platform.request("sata"), "sata_gen2", clk_freq)
         self.submodules.sata_core = LiteSATACore(self.sata_phy)
         self.submodules.sata_crossbar = LiteSATACrossbar(self.sata_core)
 
@@ -32,6 +32,10 @@ class Core(Module):
         ios = set()
 
         # Transceiver
+        for e in dir(self.sata_phy.clock_pads):
+            obj = getattr(self.sata_phy.clock_pads, e)
+            if isinstance(obj, Signal):
+                ios = ios.union({obj})
         for e in dir(self.sata_phy.pads):
             obj = getattr(self.sata_phy.pads, e)
             if isinstance(obj, Signal):

diff --git a/misoclib/mem/litesata/phy/__init__.py b/misoclib/mem/litesata/phy/__init__.py
index 3f9b1a7cccb458b0fdbb0e4ede499eed120c8e98..5df8c111699813aaa786da155752bb6c3de95f9b 100644 (file)
--- a/misoclib/mem/litesata/phy/__init__.py
+++ b/misoclib/mem/litesata/phy/__init__.py
@@ -5,6 +5,7 @@ from misoclib.mem.litesata.phy.datapath import *
 
 class LiteSATAPHY(Module):
     def __init__(self, device, clock_pads_or_refclk, pads, revision, clk_freq):
+        self.clock_pads = clock_pads_or_refclk
         self.pads = pads
         self.revision = revision