struct pipe_debug_callback *dbg,
struct iris_batch *all_batches,
enum iris_batch_name name,
- uint8_t engine)
+ uint8_t engine,
+ int priority)
{
batch->screen = screen;
batch->vtbl = vtbl;
batch->hw_ctx_id = iris_create_hw_context(screen->bufmgr);
assert(batch->hw_ctx_id);
+ iris_hw_context_set_priority(screen->bufmgr, batch->hw_ctx_id, priority);
+
util_dynarray_init(&batch->exec_fences, ralloc_context(NULL));
util_dynarray_init(&batch->syncpts, ralloc_context(NULL));
struct pipe_debug_callback *dbg,
struct iris_batch *all_batches,
enum iris_batch_name name,
- uint8_t ring);
+ uint8_t ring,
+ int priority);
void iris_chain_to_new_batch(struct iris_batch *batch);
void iris_batch_free(struct iris_batch *batch);
void iris_batch_maybe_flush(struct iris_batch *batch, unsigned estimate);
#include "iris_context.h"
#include "iris_resource.h"
#include "iris_screen.h"
+#include "common/gen_defines.h"
#include "common/gen_sample_positions.h"
/**
genX_call(devinfo, init_state, ice);
genX_call(devinfo, init_blorp, ice);
+ int priority = 0;
+ if (flags & PIPE_CONTEXT_HIGH_PRIORITY)
+ priority = GEN_CONTEXT_HIGH_PRIORITY;
+ if (flags & PIPE_CONTEXT_LOW_PRIORITY)
+ priority = GEN_CONTEXT_LOW_PRIORITY;
+
for (int i = 0; i < IRIS_BATCH_COUNT; i++) {
iris_init_batch(&ice->batches[i], screen, &ice->vtbl, &ice->dbg,
ice->batches, (enum iris_batch_name) i,
- I915_EXEC_RENDER);
+ I915_EXEC_RENDER, priority);
}
ice->vtbl.init_render_context(screen, &ice->batches[IRIS_BATCH_RENDER],
*/
return devinfo->has_llc;
+ case PIPE_CAP_CONTEXT_PRIORITY_MASK:
+ return PIPE_CONTEXT_PRIORITY_LOW |
+ PIPE_CONTEXT_PRIORITY_MEDIUM |
+ PIPE_CONTEXT_PRIORITY_HIGH;
+
// XXX: don't hardcode 00:00:02.0 PCI here
case PIPE_CAP_PCI_GROUP:
return 0;