* v850-dis.c (disassemble): Place square parentheses around second

	register operand of clr1, not1, set1 and tst1 instructions.

	* config/tc-v850.c (v850_insert_operand): Use a static buffer for
	the error message.

	* gas/v850/v850e1.d: Fix expected disassembly of clr1, not1, set1
	and tst1 insns.

diff --git a/gas/ChangeLog b/gas/ChangeLog
index 552ce4c6df7e0da01755eaf0fac4089a66139aa7..a3708e65d1d8a62b640812335e115d58e1b16398 100644 (file)
--- a/gas/ChangeLog
+++ b/gas/ChangeLog
@@ -1,3 +1,8 @@
+2012-10-04  Nick Clifton  <nickc@redhat.com>
+
+       * config/tc-v850.c (v850_insert_operand): Use a static buffer for
+       the error message.
+
 2012-10-04  Andreas Krebbel  <Andreas.Krebbel@de.ibm.com>
 
        * config/tc-s390.c (s390_parse_cpu): Add new option zEC12.

diff --git a/gas/config/tc-v850.c b/gas/config/tc-v850.c
index 3fbc654c1fddb8b23d5539f407247af909e80e5d..1340b4efa656512c22296658f8296029fa52d92b 100644 (file)
--- a/gas/config/tc-v850.c
+++ b/gas/config/tc-v850.c
@@ -1955,7 +1955,7 @@ v850_insert_operand (unsigned long insn,
 
          else if (val < (offsetT) min || val > (offsetT) max)
            {
-             char buf [128];
+             static char buf [128];
 
              /* Restore min and mix to expected values for decimal ranges.  */
              if ((operand->flags & V850_OPERAND_SIGNED)

diff --git a/gas/testsuite/ChangeLog b/gas/testsuite/ChangeLog
index 28fbd8fd0f87a8cdaf222f5e2c88461f03fca375..56b3b8a98376e0261b7a770998eb9cd56938e11b 100644 (file)
--- a/gas/testsuite/ChangeLog
+++ b/gas/testsuite/ChangeLog
@@ -1,3 +1,8 @@
+2012-10-04  Nick Clifton  <nickc@redhat.com>
+
+       * gas/v850/v850e1.d: Fix expected disassembly of clr1, not1, set1
+       and tst1 insns.
+
 2012-10-04  Andreas Krebbel  <Andreas.Krebbel@de.ibm.com>
 
        * gas/s390/zarch-zEC12.d: Fix branch preload instructions.

diff --git a/gas/testsuite/gas/v850/v850e1.d b/gas/testsuite/gas/v850/v850e1.d
index 9ba03eab7bfd4efb0c5df047f6884f323f94058d..7560d88d83657078c2beb6de7f146b295f501429 100644 (file)
--- a/gas/testsuite/gas/v850/v850e1.d
+++ b/gas/testsuite/gas/v850/v850e1.d
@@ -10,7 +10,7 @@ Disassembly of section .text:
 0x0+00 e0 0f 42 13 [   ]*bsh   r1, r2
 0x0+04 e0 1f 40 23 [   ]*bsw   sp, gp
 0x0+08 05 02  [        ]*callt 5
-0x0+0a e8 3f e4 00 [   ]*clr1  r7, r8
+0x0+0a e8 3f e4 00 [   ]*clr1  r7, \[r8\]
 0x0+0e f6 17 14 1b [   ]*cmov  nz, -10, r2, sp
 0x0+12 e1 17 34 1b [   ]*cmov  nz, r1, r2, sp
 0x0+16 e0 07 44 01 [   ]*ctret 
@@ -30,16 +30,16 @@ Disassembly of section .text:
 0x0+4e e1 17 20 1a [   ]*mul   r1, r2, sp
 0x0+52 e4 2f 22 32 [   ]*mulu  gp, r5, r6
 0x0+56 e3 2f 46 32 [   ]*mulu  35, r5, r6
-0x0+5a ea 4f e2 00 [   ]*not1  r9, r10
+0x0+5a ea 4f e2 00 [   ]*not1  r9, \[r10\]
 0x0+5e a8 07 01 80 [   ]*prepare       {r24}, 20
 0x0+62 a8 07 03 70 [   ]*prepare       {r25 - r27}, 20, sp
-0x0+66 e1 4f e0 00 [   ]*set1  r9, r1
+0x0+66 e1 4f e0 00 [   ]*set1  r9, \[r1\]
 0x0+6a ea 47 00 02 [   ]*sasf  nz, r8
 0x0+6e 60 20  [        ]*sld.bu        0\[ep\], gp
 0x0+70 77 28  [        ]*sld.hu        14\[ep\], r5
 0x0+72 a1 00  [        ]*sxb   r1
 0x0+74 e2 00  [        ]*sxh   r2
-0x0+76 ff 07 e6 00 [   ]*tst1  r0, lp
+0x0+76 ff 07 e6 00 [   ]*tst1  r0, \[lp\]
 0x0+7a 83 00  [        ]*zxb   sp
 0x0+7c c4 00  [        ]*zxh   gp
 0x0+7e 63 ff 9d 00[    ]*st.w  lp, 156\[sp\]

diff --git a/opcodes/ChangeLog b/opcodes/ChangeLog
index 1400e05fbe0b09bcdb75aa5da1b4b50c43df7282..214ea8192a38708a3120196a8eac22ed8e428220 100644 (file)
--- a/opcodes/ChangeLog
+++ b/opcodes/ChangeLog
@@ -1,3 +1,8 @@
+2012-10-04  Nick Clifton  <nickc@redhat.com>
+
+       * v850-dis.c (disassemble): Place square parentheses around second
+       register operand of clr1, not1, set1 and tst1 instructions.
+
 2012-10-04  Andreas Krebbel  <Andreas.Krebbel@de.ibm.com>
 
        * s390-mkopc.c: Support new option zEC12.
@@ -11,8 +16,8 @@
 
 2012-09-25  Saravanan Ekanathan <saravanan.ekanathan@amd.com>
 
-       * i386-gen.c (cpu_flag_init): Add missing Cpu flags in 
-       CPU_BDVER1_FLAGS, CPU_BDVER2_FLAGS, CPU_BTVER1_FLAGS 
+       * i386-gen.c (cpu_flag_init): Add missing Cpu flags in
+       CPU_BDVER1_FLAGS, CPU_BDVER2_FLAGS, CPU_BTVER1_FLAGS
        and CPU_BTVER2_FLAGS.
        * i386-init.h: Regenerated.
 

diff --git a/opcodes/v850-dis.c b/opcodes/v850-dis.c
index 60b452bf79c6776f080303e28f36af5eea1d6528..5f9d87b8f8668ce5beb7a2ed7443e39ecf966acb 100644 (file)
--- a/opcodes/v850-dis.c
+++ b/opcodes/v850-dis.c
@@ -309,9 +309,11 @@ disassemble (bfd_vma memaddr, struct disassemble_info *info, int bytes_read, uns
                   We may need to output a trailing ']' if the last operand
                   in an instruction is the register for a memory address.
 
-                  The exception (and there's always an exception) is the
+                  The exception (and there's always an exception) are the
                   "jmp" insn which needs square brackets around it's only
-                  register argument.  */
+                  register argument, and the clr1/not1/set1/tst1 insns
+                  which [...] around their second register argument.  */
+
              prefix = "";
              if (operand->flags & V850_OPERAND_BANG)
                {
@@ -334,6 +336,16 @@ disassemble (bfd_vma memaddr, struct disassemble_info *info, int bytes_read, uns
                  info->fprintf_func (info->stream, "%s[", prefix);
                  square = TRUE;
                }
+             else if (opnum == 2
+                      && (   op->opcode == 0x00e407e0 /* clr1 */
+                          || op->opcode == 0x00e207e0 /* not1 */
+                          || op->opcode == 0x00e007e0 /* set1 */
+                          || op->opcode == 0x00e607e0 /* tst1 */
+                          ))
+               {
+                 info->fprintf_func (info->stream, ", %s[", prefix);
+                 square = TRUE;
+               }               
              else if (opnum > 1)
                info->fprintf_func (info->stream, ", %s", prefix);