whitespace additions on lbzu to make more like PDF,

also added brackets around regs

diff --git a/openpower/isa/fixedload.mdwn b/openpower/isa/fixedload.mdwn
index 93297dccdb819a58e7fd6cee4780f619375616f9..20252b28088b80d39b6ae712ec8d031b149b96aa 100644 (file)
--- a/openpower/isa/fixedload.mdwn
+++ b/openpower/isa/fixedload.mdwn
@@ -76,10 +76,14 @@ Pseudo-code:
     RT <- ([0] * (XLEN-8)) || MEM(EA, 1)
     RA <- EA
 
-Description:Let the effective address (EA) be the sum (RA)+ D. The
-byte in storage addressed by EA is loaded into RT 56:63.
-RT0:55 are set to 0.
+Description:
+
+Let the effective address (EA) be the sum (RA)+ D. The
+byte in storage addressed by EA is loaded into RT[56:63].
+RT[0:55] are set to 0.
+
 EA is placed into register RA.
+
 If RA=0 or RA=RT, the instruction form is invalid.
 
 Special Registers Altered: