add MSR to verilator output debug reporting

diff --git a/core.vhdl b/core.vhdl
index b33086b7a30e98b0f9b99b412616b77df1ad0722..f5638c899a7bc32c6571c27b595856a564532715 100644 (file)
--- a/core.vhdl
+++ b/core.vhdl
@@ -45,6 +45,7 @@ entity core is
     -- for verilator debugging
     nia_req: out std_ulogic;
     nia: out std_ulogic_vector(63 downto 0);
+    msr_o: out std_ulogic_vector(63 downto 0);
     insn: out std_ulogic_vector(31 downto 0)
         );
 end core;
@@ -442,6 +443,7 @@ begin
 
     -- snoop and report instruction being executed
     nia <= icache_to_decode1.nia;
+    msr_o <= msr;
     insn <= icache_to_decode1.insn;
     nia_req <= icache_to_decode1.valid and fetch1_to_icache.sequential;
 

diff --git a/fpga/top-generic.vhdl b/fpga/top-generic.vhdl
index 4524a368f7475d242413f7826decc2fa267d1b9b..32bdfcec2f19d7a294d73d31cacbd865494c7d4e 100644 (file)
--- a/fpga/top-generic.vhdl
+++ b/fpga/top-generic.vhdl
@@ -41,6 +41,7 @@ entity toplevel is
     -- for verilator debugging
     nia_req: out std_ulogic;
     nia: out std_ulogic_vector(63 downto 0);
+    msr_o: out std_ulogic_vector(63 downto 0);
     insn: out std_ulogic_vector(31 downto 0)
 
        );
@@ -113,6 +114,7 @@ begin
         bram_sel            => bram_sel,
         nia_req           => nia_req,
         nia               => nia,
+        msr_o             => msr_o,
         insn              => insn
            );
 

diff --git a/soc.vhdl b/soc.vhdl
index 8440f54db46ee7224a2ef8e586d9882783b02b45..22122479059c371132d5312c478522eb7f3913d4 100644 (file)
--- a/soc.vhdl
+++ b/soc.vhdl
@@ -122,6 +122,7 @@ entity soc is
     -- for verilator debugging
     nia_req: out std_ulogic;
     nia: out std_ulogic_vector(63 downto 0);
+    msr_o: out std_ulogic_vector(63 downto 0);
     insn: out std_ulogic_vector(31 downto 0)
        );
 end entity soc;
@@ -275,6 +276,7 @@ architecture behaviour of soc is
         terminated_out   : out std_logic;
         -- for verilator debugging
         nia_req: out std_ulogic;
+        msr_o: out std_ulogic_vector(63 downto 0);
         nia: out std_ulogic_vector(63 downto 0);
         insn: out std_ulogic_vector(31 downto 0)
         );
@@ -325,6 +327,7 @@ begin
            ext_irq => core_ext_irq,
         nia_req           => nia_req,
         nia               => nia,
+        msr_o             => msr_o,
         insn              => insn
            );
     end generate;
@@ -348,6 +351,7 @@ begin
            ext_irq => core_ext_irq,
         nia_req           => nia_req,
         nia               => nia,
+        msr_o             => msr_o,
         insn              => insn
            );
     end generate;

diff --git a/verilator/microwatt-verilator.cpp b/verilator/microwatt-verilator.cpp
index a409c6e1cc8c6f8f0bf1b038c5e3474836b80049..b75eb528373caf0f5e542fd88afed57be14bb2af 100644 (file)
--- a/verilator/microwatt-verilator.cpp
+++ b/verilator/microwatt-verilator.cpp
@@ -197,7 +197,8 @@ int main(int argc, char **argv)
 
 #ifdef BRAM_DEBUG
         if (top->nia_req) {
-            fprintf(dump, "pc %8x insn %8x\n", top->nia, top->insn);
+            fprintf(dump, "pc %8x insn %8x msr %16lx\n",
+                                top->nia, top->insn, top->msr_o);
         }
         if (top->bram_we) {
             fprintf(dump, "                          " \