dev: Update port terminology

Change-Id: I48bd6718471f034f7c3226279efe7ada0d9c81e9
Reviewed-on: https://gem5-review.googlesource.com/c/public/gem5/+/32315
Reviewed-by: Giacomo Travaglini <giacomo.travaglini@arm.com>
Reviewed-by: Gabe Black <gabeblack@google.com>
Maintainer: Giacomo Travaglini <giacomo.travaglini@arm.com>
Maintainer: Gabe Black <gabeblack@google.com>
Tested-by: kokoro <noreply+kokoro@google.com>

diff --git a/src/dev/Device.py b/src/dev/Device.py
index 8950763e39ba80497da01018d2b73a25412f3bd2..d9f351da36a22647b9adcafb30ef5d15064c2cbe 100644 (file)
--- a/src/dev/Device.py
+++ b/src/dev/Device.py
@@ -46,7 +46,7 @@ class PioDevice(ClockedObject):
     type = 'PioDevice'
     cxx_header = "dev/io_device.hh"
     abstract = True
-    pio = SlavePort("Programmed I/O port")
+    pio = ResponsePort("Programmed I/O port")
     system = Param.System(Parent.any, "System this device is part of")
 
     def generateBasicPioDeviceNode(self, state, name, pio_addr,
@@ -79,7 +79,7 @@ class DmaDevice(PioDevice):
     type = 'DmaDevice'
     cxx_header = "dev/dma_device.hh"
     abstract = True
-    dma = MasterPort("DMA port")
+    dma = RequestPort("DMA port")
 
     _iommu = None
 

diff --git a/src/dev/arm/Gic.py b/src/dev/arm/Gic.py
index 59ade75afb244db334f433463fc6914a7b7b97fd..e2229b85b69c9cfba6b78284593184f5de6563ed 100644 (file)
--- a/src/dev/arm/Gic.py
+++ b/src/dev/arm/Gic.py
@@ -177,7 +177,7 @@ class Gicv3Its(BasicPioDevice):
     type = 'Gicv3Its'
     cxx_header = "dev/arm/gic_v3_its.hh"
 
-    dma = MasterPort("DMA port")
+    dma = RequestPort("DMA port")
     pio_size = Param.Unsigned(0x20000, "Gicv3Its pio size")
 
     # CIL [36] = 0: ITS supports 16-bit CollectionID

diff --git a/src/dev/arm/SMMUv3.py b/src/dev/arm/SMMUv3.py
index 5be09de6f1c21c0021e0eadf05d670dba9c168b8..0b9ab2128ec166f3aa1b92574bfa6df16ac426fc 100644 (file)
--- a/src/dev/arm/SMMUv3.py
+++ b/src/dev/arm/SMMUv3.py
@@ -43,9 +43,9 @@ class SMMUv3SlaveInterface(ClockedObject):
     type = 'SMMUv3SlaveInterface'
     cxx_header = 'dev/arm/smmu_v3_slaveifc.hh'
 
-    slave = SlavePort('Device port')
-    ats_master = MasterPort('ATS master port')
-    ats_slave  = SlavePort('ATS slave port')
+    slave = ResponsePort('Device port')
+    ats_master = RequestPort('ATS master port')
+    ats_slave  = ResponsePort('ATS slave port')
 
     port_width = Param.Unsigned(16, 'Port width in bytes (= 1 beat)')
     wrbuf_slots = Param.Unsigned(16, 'Write buffer size (in beats)')
@@ -74,10 +74,11 @@ class SMMUv3(ClockedObject):
     type = 'SMMUv3'
     cxx_header = 'dev/arm/smmu_v3.hh'
 
-    master = MasterPort('Master port')
-    master_walker = MasterPort(
+    master = RequestPort('Master port')
+    master_walker = RequestPort(
         'Master port for SMMU initiated HWTW requests (optional)')
-    control = SlavePort('Control port for accessing memory-mapped registers')
+    control = ResponsePort(
+        'Control port for accessing memory-mapped registers')
     sample_period = Param.Clock('10us', 'Stats sample period')
     reg_map = Param.AddrRange('Address range for control registers')
     system = Param.System(Parent.any, "System this device is part of")

diff --git a/src/dev/arm/gic_v3_its.hh b/src/dev/arm/gic_v3_its.hh
index 8575f7ee314822b2ea97879498a4a51b9f0e2140..54beb3ef6843fa676c551e129b536b29c445eb5a 100644 (file)
--- a/src/dev/arm/gic_v3_its.hh
+++ b/src/dev/arm/gic_v3_its.hh
@@ -77,14 +77,14 @@ class Gicv3Its : public BasicPioDevice
     friend class ::ItsTranslation;
     friend class ::ItsCommand;
   public:
-    class DataPort : public MasterPort
+    class DataPort : public RequestPort
     {
       protected:
         Gicv3Its &its;
 
       public:
         DataPort(const std::string &_name, Gicv3Its &_its) :
-            MasterPort(_name, &_its),
+            RequestPort(_name, &_its),
             its(_its)
         {}
 

diff --git a/src/dev/arm/smmu_v3_ports.cc b/src/dev/arm/smmu_v3_ports.cc
index f972fcfdc3b9ff89774f33489cf8db96df31050e..3f542502120e8ec0b92562a275d8343e74d04f62 100644 (file)
--- a/src/dev/arm/smmu_v3_ports.cc
+++ b/src/dev/arm/smmu_v3_ports.cc
@@ -42,7 +42,7 @@
 #include "dev/arm/smmu_v3_slaveifc.hh"
 
 SMMUMasterPort::SMMUMasterPort(const std::string &_name, SMMUv3 &_smmu) :
-    MasterPort(_name, &_smmu),
+    RequestPort(_name, &_smmu),
     smmu(_smmu)
 {}
 
@@ -60,7 +60,7 @@ SMMUMasterPort::recvReqRetry()
 
 SMMUMasterTableWalkPort::SMMUMasterTableWalkPort(const std::string &_name,
                                                  SMMUv3 &_smmu) :
-    MasterPort(_name, &_smmu),
+    RequestPort(_name, &_smmu),
     smmu(_smmu)
 {}
 

diff --git a/src/dev/arm/smmu_v3_ports.hh b/src/dev/arm/smmu_v3_ports.hh
index 9d54f138098d226471a000c6cc490e49554401a4..ee68bbb874c2b1cb3ac019a9786cc2ae22b0830d 100644 (file)
--- a/src/dev/arm/smmu_v3_ports.hh
+++ b/src/dev/arm/smmu_v3_ports.hh
@@ -44,7 +44,7 @@
 class SMMUv3;
 class SMMUv3SlaveInterface;
 
-class SMMUMasterPort : public MasterPort
+class SMMUMasterPort : public RequestPort
 {
   protected:
     SMMUv3 &smmu;
@@ -58,7 +58,7 @@ class SMMUMasterPort : public MasterPort
 };
 
 // Separate master port to send MMU initiated requests on
-class SMMUMasterTableWalkPort : public MasterPort
+class SMMUMasterTableWalkPort : public RequestPort
 {
   protected:
     SMMUv3 &smmu;

diff --git a/src/dev/dma_device.cc b/src/dev/dma_device.cc
index 63642c905187c782c29ecf4b9bfb269b301d4456..03882e320f9ee02450bc693b87a710f88aaa9c2a 100644 (file)
--- a/src/dev/dma_device.cc
+++ b/src/dev/dma_device.cc
@@ -51,7 +51,7 @@
 
 DmaPort::DmaPort(ClockedObject *dev, System *s,
                  uint32_t sid, uint32_t ssid)
-    : MasterPort(dev->name() + ".dma", dev),
+    : RequestPort(dev->name() + ".dma", dev),
       device(dev), sys(s), masterId(s->getMasterId(dev)),
       sendEvent([this]{ sendDma(); }, dev->name()),
       pendingCount(0), inRetry(false),

diff --git a/src/dev/dma_device.hh b/src/dev/dma_device.hh
index 810519566247da6d347040cbc57168f24fa20f09..56c8d4ca502d7756695396fc4c3e53839703256a 100644 (file)
--- a/src/dev/dma_device.hh
+++ b/src/dev/dma_device.hh
@@ -52,7 +52,7 @@
 
 class ClockedObject;
 
-class DmaPort : public MasterPort, public Drainable
+class DmaPort : public RequestPort, public Drainable
 {
   private:
 

diff --git a/src/dev/x86/I82094AA.py b/src/dev/x86/I82094AA.py
index b2aa7bf3ce6deacdb68fcb10647de51717c3e73b..2cb210aba67dfa1bb7193433924d3e47f3e88c14 100644 (file)
--- a/src/dev/x86/I82094AA.py
+++ b/src/dev/x86/I82094AA.py
@@ -34,7 +34,7 @@ class I82094AA(BasicPioDevice):
     cxx_class = 'X86ISA::I82094AA'
     cxx_header = "dev/x86/i82094aa.hh"
     apic_id = Param.Int(1, 'APIC id for this IO APIC')
-    int_master = MasterPort("Port for sending interrupt messages")
+    int_master = RequestPort("Port for sending interrupt messages")
     int_latency = Param.Latency('1ns', \
             "Latency for an interrupt to propagate through this device.")
     external_int_pic = Param.I8259(NULL, "External PIC, if any")