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Add missing changelog item
author
Miodrag Milanovic
<mmicko@gmail.com>
Fri, 5 Nov 2021 09:08:50 +0000
(10:08 +0100)
committer
Miodrag Milanovic
<mmicko@gmail.com>
Fri, 5 Nov 2021 09:08:50 +0000
(10:08 +0100)
CHANGELOG
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diff --git
a/CHANGELOG
b/CHANGELOG
index 6feea416251676239699a3fecad0dcf3ead1a9d4..e351591233a807acd35fc3e5cdfa9518d45c1fa7 100644
(file)
--- a/
CHANGELOG
+++ b/
CHANGELOG
@@
-21,6
+21,7
@@
Yosys 0.10 .. Yosys 0.10-dev
- Importer support for PRIM_BUFIF1
- Option to use Verific without VHDL support
- Importer support for {PRIM,WIDE_OPER}_DLATCH{,RS}
+ - Added -cfg option for getting/setting Verific runtime flags
Yosys 0.9 .. Yosys 0.10
--------------------------