power_insn: support common branch disassembly

diff --git a/src/openpower/decoder/power_insn.py b/src/openpower/decoder/power_insn.py
index 5fc8f00cfc31beefca6d09c1118720e585e3b6bd..073d4d7798d0fe3c78506160c1012dfb80a29595 100644 (file)
--- a/src/openpower/decoder/power_insn.py
+++ b/src/openpower/decoder/power_insn.py
@@ -1733,6 +1733,20 @@ class BranchBaseRM(SZBaseRM, BaseRM):
     CTR: BaseRM[19]
     VLS: BaseRM[20]
 
+    def specifiers(self, record):
+        if self.ALL:
+            yield "all"
+        if self.SNZ:
+            yield "snz"
+        if self.SL:
+            yield "sl"
+        if self.SLu:
+            yield "slu"
+        if self.LRu:
+            yield "lru"
+
+        yield from super().specifiers(record=record)
+
 
 class BranchSimpleRM(BranchBaseRM):
     """branch: simple mode"""

diff --git a/src/openpower/sv/trans/test_pysvp64dis.py b/src/openpower/sv/trans/test_pysvp64dis.py
index f3f014f8e143c7d99b85d249ccff69c9905314cd..53d854ca4599267d342af67b708344b83d855378 100644 (file)
--- a/src/openpower/sv/trans/test_pysvp64dis.py
+++ b/src/openpower/sv/trans/test_pysvp64dis.py
@@ -255,6 +255,15 @@ class SVSTATETestCase(unittest.TestCase):
                         ]
         self._do_tst(expected)
 
+    def test_16_bc(self):
+        expected = [
+                    "sv.bc/all 12,*1,0xc",
+                    "sv.bc/snz 12,*1,0xc",
+                    "sv.bc/all/sl/slu 12,*1,0xc",
+                    "sv.bc/all/snz/sl/slu/lru 12,*1,0xc",
+                        ]
+        self._do_tst(expected)
+
 if __name__ == "__main__":
     unittest.main()