Merge remote-tracking branch 'origin/master' into xaig_dff

diff --cc backends/aiger/xaiger.cc
index 632a5c8d5691a28841cfd0569d232bb74b975ec8,69f63486c8605a39c0b971c7e5cf7f7d368487b4..a1085addf3798a3a8cc09f360c8465da8905443d
--- 1/backends/aiger/xaiger.cc
--- 2/backends/aiger/xaiger.cc
+++ b/backends/aiger/xaiger.cc
@@@ -250,17 -240,7 +256,17 @@@ struct XAigerWrite
  
                        log_assert(!holes_mode);
  
-                       RTLIL::Module* inst_module = !holes_mode ? module->design->module(cell->type) : nullptr;
 +                      if (cell->type == "$__ABC_FF_")
 +                      {
 +                              SigBit D = sigmap(cell->getPort("\\D").as_bit());
 +                              SigBit Q = sigmap(cell->getPort("\\Q").as_bit());
 +                              unused_bits.erase(D);
 +                              undriven_bits.erase(Q);
 +                              alias_map[Q] = D;
 +                              continue;
 +                      }
 +
+                       RTLIL::Module* inst_module = module->design->module(cell->type);
                        if (inst_module && inst_module->attributes.count("\\abc_box_id")) {
                                abc_box_seen = true;
  

diff --cc techlibs/xilinx/Makefile.inc
index 860fcd88c18754880b648d7ae18c90d785039606,17c5df37d8c925deb06e2f0559fd5f08df8bda6d..c9a3a49fb46c60212ef1be94303e4f93f952b474
--- 1/techlibs/xilinx/Makefile.inc
--- 2/techlibs/xilinx/Makefile.inc
+++ b/techlibs/xilinx/Makefile.inc
@@@ -30,8 -30,8 +30,9 @@@ $(eval $(call add_share_file,share/xili
  $(eval $(call add_share_file,share/xilinx,techlibs/xilinx/arith_map.v))
  $(eval $(call add_share_file,share/xilinx,techlibs/xilinx/ff_map.v))
  $(eval $(call add_share_file,share/xilinx,techlibs/xilinx/lut_map.v))
+ $(eval $(call add_share_file,share/xilinx,techlibs/xilinx/mux_map.v))
  
 +$(eval $(call add_share_file,share/xilinx,techlibs/xilinx/abc_ff.v))
  $(eval $(call add_share_file,share/xilinx,techlibs/xilinx/abc_xc7.box))
  $(eval $(call add_share_file,share/xilinx,techlibs/xilinx/abc_xc7.lut))
  $(eval $(call add_share_file,share/xilinx,techlibs/xilinx/abc_xc7_nowide.lut))

diff --cc techlibs/xilinx/abc_xc7.box
index 633e2d484303563d1f34f52f0a632456c4c5797a,3789ff350ab479dd07dc7e0786567af02796c070..69ff9aeab20a2c1f52a7c2bc35e1cf9470948fe7
--- 1/techlibs/xilinx/abc_xc7.box
--- 2/techlibs/xilinx/abc_xc7.box
+++ b/techlibs/xilinx/abc_xc7.box
@@@ -48,26 -53,6 +53,26 @@@ RAM64X1D 6 0 15 
  # SLICEM/A6LUT + F7[AB]MUX
  # Inputs: A0 A1 A2 A3 A4 A5 A6 D DPRA0 DPRA1 DPRA2 DPRA3 DPRA4 DPRA5 DPRA6 WCLK WE
  # Outputs: DPO SPO
- RAM128X1D 6 0 17 2
+ RAM128X1D 7 0 17 2
  -    -    -   -   -   -   -   - 1009 998 839 774 605 494 450 - -
  1047 1036 877 812 643 532 478 - -    -   -   -   -   -   -   - -
 +
 +# Inputs: C CE D R \$pastQ
 +# Outputs: Q
 +FDRE 7 1 5 1
 +- 109 -46 358 0
 +
 +# Inputs: C CE D S \$pastQ
 +# Outputs: Q
 +FDSE 8 0 5 1
 +- 109 -46 358 0
 +
 +# Inputs: C CE CLR D \$pastQ
 +# Outputs: Q
 +FDCE 9 0 5 1
 +- 109 - -46 0
 +
 +# Inputs: C CE D PRE \$pastQ
 +# Outputs: Q
 +FDPE 10 0 5 1
 +- 109 -46 - 0

diff --cc techlibs/xilinx/synth_xilinx.cc
index cdc64db1d73b24fe64fb7bd31ca316e418357ea2,77daa745c8672f39cf2304988c9bc65a119049b4..2455c2885c84056920bcbb121e0392cb7917244c
--- 1/techlibs/xilinx/synth_xilinx.cc
--- 2/techlibs/xilinx/synth_xilinx.cc
+++ b/techlibs/xilinx/synth_xilinx.cc
@@@ -299,11 -372,10 +372,11 @@@ struct SynthXilinxPass : public ScriptP
                        else if (abc9) {
                                if (family != "xc7")
                                        log_warning("'synth_xilinx -abc9' currently supports '-family xc7' only.\n");
 +                              run("read_verilog -icells -lib +/xilinx/abc_ff.v");
                                if (nowidelut)
-                                       run("abc9 -lut +/xilinx/abc_xc7_nowide.lut -box +/xilinx/abc_xc7.box -W " + std::string(XC7_WIRE_DELAY) + string(retime ? " -dff" : ""));
+                                       run("abc9 -lut +/xilinx/abc_xc7_nowide.lut -box +/xilinx/abc_xc7.box -W " + std::to_string(XC7_WIRE_DELAY));
                                else
-                                       run("abc9 -lut +/xilinx/abc_xc7.lut -box +/xilinx/abc_xc7.box -W " + std::string(XC7_WIRE_DELAY) + string(retime ? " -dff" : ""));
+                                       run("abc9 -lut +/xilinx/abc_xc7.lut -box +/xilinx/abc_xc7.box -W " + std::to_string(XC7_WIRE_DELAY));
                        }
                        else {
                                if (nowidelut)