set Tercel to default into Quad SPI mode

diff --git a/tercel/wishbone_spi_master.v b/tercel/wishbone_spi_master.v
index 4cf64fa93de9ced02c2ca4a755fb63eee4358da2..c4aa9045a9b8f3f9490956d4f20b615e71e0c13b 100644 (file)
--- a/tercel/wishbone_spi_master.v
+++ b/tercel/wishbone_spi_master.v
@@ -65,8 +65,10 @@ module tercel_core(
        wire [31:0] device_version;
 
        // PHY configuration register 1
-       // Defaults to standard SPI mode, 3BA, non-extended read/write (qspi_[read|write]_quad_io_en = 0), cs_extra_idle_cycles = 0, dummy cycle cont = 10, clock divisor 16
-       reg [31:0] phy_cfg1 = 32'h00000a10;
+       // Defaults to Quad SPI mode, 3BA,
+    // non-extended read/write (qspi_[read|write]_quad_io_en = 0),
+    // cs_extra_idle_cycles = 0, dummy cycle cont = 10, clock divisor 16
+       reg [31:0] phy_cfg1 = 32'h00020a10;
 
        // Defaults to compatibility with Micron N25Q/512MB and similar 3BA/4BA capable devices, with multicycle and write disabled
        // Note that the N25Q does not support normal reads in QSPI mode, so we leave the QSPI normal read commands equal