panfrost/midgard: Reenable pipeline register creation

This was disabled to permit regression-free RA work. Now that the spill
code is in place, we can reenable, with some caveats about efficacy.

Signed-off-by: Alyssa Rosenzweig <alyssa.rosenzweig@collabora.com>

diff --git a/src/panfrost/midgard/midgard_schedule.c b/src/panfrost/midgard/midgard_schedule.c
index 862b9306c15ca069dcc011157be4db93d20fe83d..84b7b1be023362220eb21bfa238c07b45bca565f 100644 (file)
--- a/src/panfrost/midgard/midgard_schedule.c
+++ b/src/panfrost/midgard/midgard_schedule.c
@@ -769,19 +769,18 @@ schedule_program(compiler_context *ctx)
                 g = allocate_registers(ctx, &spilled);
         } while(spilled && ((iter_count--) > 0));
 
-                /* We would like to run RA after scheduling, but spilling can
-                 * complicate this */
+        /* After RA finishes, we schedule all at once */
 
-                mir_foreach_block(ctx, block) {
-                        schedule_block(ctx, block);
-                }
-#if 0
-
-                /* Pipeline registers creation is a prepass before RA */
-                mir_create_pipeline_registers(ctx);
-#endif
+        mir_foreach_block(ctx, block) {
+                schedule_block(ctx, block);
+        }
 
+        /* Finally, we create pipeline registers as a peephole pass after
+         * scheduling. This isn't totally optimal, since there are cases where
+         * the usage of pipeline registers can eliminate spills, but it does
+         * save some power */
 
+        mir_create_pipeline_registers(ctx);
 
         if (iter_count <= 0) {
                 fprintf(stderr, "panfrost: Gave up allocating registers, rendering will be incomplete\n");