({add,sub}di{_mem,3}): Patterns merged.

From-SVN: r9926

diff --git a/gcc/config/m68k/m68k.md b/gcc/config/m68k/m68k.md
index db632e6aa57c1e7c8a984e6c1253d36d7d0aa5fa..2e2f7791205dd4f931f226b05f4d77dfe1723ac9 100644 (file)
--- a/gcc/config/m68k/m68k.md
+++ b/gcc/config/m68k/m68k.md
@@ -2050,57 +2050,57 @@
   return \"add%.l %1,%0\";
 } ")
 
-(define_insn "adddi_mem"
-  [(set (match_operand:DI 0 "general_operand" "=o,<,>")
-       (plus:DI (match_operand:DI 1 "general_operand" "%0,0,0")
-                (match_operand:DI 2 "general_operand" "d,d,d")))
-   (clobber (match_scratch:SI 3 "=d,d,d"))]
-  ""
-  "*
-{
-  CC_STATUS_INIT;
-  operands[4] = gen_rtx (REG, SImode, REGNO (operands[2]) + 1);
-  if (which_alternative == 2)
-    {
-      operands[1] = gen_rtx (MEM, SImode,
-              gen_rtx (PLUS, VOIDmode, XEXP(operands[0], 0),
-                       gen_rtx (CONST_INT, VOIDmode, -8)));
-      return \"move%.l %0,%3\;add%.l %4,%0\;addx%.l %2,%3\;move%.l %3,%1\";
-    }
-  if (which_alternative == 1)
-    {
-      operands[1] = XEXP(operands[0], 0);
-      return \"add%.l %4,%0\;move%.l %0,%3\;addx%.l %2,%3\;move%.l %3,%1\";
-    }
-  operands[1] = adj_offsettable_operand (operands[0], 4);
-  return \"add%.l %4,%1\;move%.l %0,%3\;addx%.l %2,%3\;move%.l %3,%0\";
-} ")
-
 (define_insn "adddi3"
-  [(set (match_operand:DI 0 "general_operand" "=d,d,d,<")
+  [(set (match_operand:DI 0 "general_operand" "=d,<,d,o<>")
        (plus:DI (match_operand:DI 1 "general_operand" "%0,0,0,0")
-                (match_operand:DI 2 "general_operand" "*ao,>,d,<")))]
+                (match_operand:DI 2 "general_operand" "d,<,*ao>,d")))
+   (clobber (match_scratch:SI 3 "=X,X,d,d"))]
   ""
   "*
 {
-  if (which_alternative == 3)
-    return \"add%.l %2,%0\;addx%.l %2,%0\";
-  operands[1] = gen_rtx (REG, SImode, REGNO (operands[0]) + 1);
-  if (which_alternative == 1)
+  if (DATA_REG_P (operands[0]))
     {
+      if (DATA_REG_P (operands[2]))
+       return \"add%.l %R2,%R0\;addx%.l %2,%0\";
+      else if (GET_CODE (operands[2]) == MEM
+         && GET_CODE (XEXP (operands[2], 0)) == POST_INC)
+       {
+         return \"move%.l %2,%3\;add%.l %2,%R0\;addx%.l %3,%0\";
+       }
+      else
+       {
+         /* TODO : this should work also for CONST operands[2] */
+         if (GET_CODE (operands[2]) == REG)
+           operands[1] = gen_rtx (REG, SImode, REGNO (operands[2]) + 1);
+         else
+           operands[1] = adj_offsettable_operand (operands[2], 4);
+         return \"move%.l %2,%3\;add%.l %1,%R0\;addx%.l %3,%0\";
+       }
+    }
+  else if (GET_CODE (operands[0]) == MEM)
+    {
+      if (GET_CODE (operands[2]) == MEM
+         && GET_CODE (XEXP (operands[2], 0)) == PRE_DEC)
+       return \"add%.l %2,%0\;addx%.l %2,%0\";
       CC_STATUS_INIT;
-      return \"add%.l %2,%0\;add%.l %2,%1\;negx%.l %0\;neg%.l %0\";
+      if (GET_CODE (XEXP (operands[0], 0)) == POST_INC)
+       {
+         operands[1] = gen_rtx (MEM, SImode,
+                  gen_rtx (PLUS, VOIDmode, XEXP(operands[0], 0),
+                           gen_rtx (CONST_INT, VOIDmode, -8)));
+         return \"move%.l %0,%3\;add%.l %R2,%0\;addx%.l %2,%3\;move%.l %3,%1\";
+       }
+      else if (GET_CODE (XEXP (operands[0], 0)) == PRE_DEC)
+       {
+         operands[1] = XEXP(operands[0], 0);
+         return \"add%.l %R2,%0\;move%.l %0,%3\;addx%.l %2,%3\;move%.l %3,%1\";
+       }
+      else
+       {
+         operands[1] = adj_offsettable_operand (operands[0], 4);
+         return \"add%.l %R2,%1\;move%.l %0,%3\;addx%.l %2,%3\;move%.l %3,%0\";
+       }
     }
-  if (GET_CODE (operands[2]) == REG)
-    operands[3] = gen_rtx (REG, SImode, REGNO (operands[2]) + 1);
-  else
-    operands[3] = adj_offsettable_operand (operands[2], 4);
-  if (which_alternative == 2)
-    return \"add%.l %3,%1\;addx%.l %2,%0\";
-  CC_STATUS_INIT;
-  /* negx + neg simulates (non-existent) addx #0 */
-  /* TODO : this should work also for CONST operands[2] */
-  return \"add%.l %3,%1\;negx%.l %0\;neg%.l %0\;add%.l %2,%0\";
 } ")
 
 (define_insn "addsi_lshrsi_31"
@@ -2639,57 +2639,57 @@
   return \"sub%.l %1,%0\";
 } ")
 
-(define_insn "subdi_mem"
-  [(set (match_operand:DI 0 "general_operand" "=o,<,>")
-       (minus:DI (match_operand:DI 1 "general_operand" "0,0,0")
-                (match_operand:DI 2 "register_operand" "d,d,d")))
-   (clobber (match_scratch:SI 3 "=d,d,d"))]
+(define_insn "subdi3"
+  [(set (match_operand:DI 0 "general_operand" "=d,<,d,o<>")
+       (minus:DI (match_operand:DI 1 "general_operand" "%0,0,0,0")
+                (match_operand:DI 2 "general_operand" "d,<,*ao>,d")))
+   (clobber (match_scratch:SI 3 "=X,X,d,d"))]
   ""
   "*
 {
-  CC_STATUS_INIT;
-  operands[4] = gen_rtx (REG, SImode, REGNO (operands[2]) + 1);
-  if (which_alternative == 2)
+  if (DATA_REG_P (operands[0]))
     {
-      operands[1] = gen_rtx (MEM, SImode,
-              gen_rtx (PLUS, VOIDmode, XEXP(operands[0], 0),
-                       gen_rtx (CONST_INT, VOIDmode, -8)));
-      return \"move%.l %0,%3\;sub%.l %4,%0\;subx%.l %2,%3\;move%.l %3,%1\";
+      if (DATA_REG_P (operands[2]))
+       return \"sub%.l %R2,%R0\;subx%.l %2,%0\";
+      else if (GET_CODE (operands[2]) == MEM
+         && GET_CODE (XEXP (operands[2], 0)) == POST_INC)
+       {
+         return \"move%.l %2,%3\;sub%.l %2,%R0\;subx%.l %3,%0\";
+       }
+      else
+       {
+         /* TODO : this should work also for CONST operands[2] */
+         if (GET_CODE (operands[2]) == REG)
+           operands[1] = gen_rtx (REG, SImode, REGNO (operands[2]) + 1);
+         else
+           operands[1] = adj_offsettable_operand (operands[2], 4);
+         return \"move%.l %2,%3\;sub%.l %1,%R0\;subx%.l %3,%0\";
+       }
     }
-  if (which_alternative == 1)
-    {
-      operands[1] = XEXP(operands[0], 0);
-      return \"sub%.l %4,%0\;move%.l %0,%3\;subx%.l %2,%3\;move%.l %3,%1\";
-    }
-  operands[1] = adj_offsettable_operand (operands[0], 4);
-  return \"sub%.l %4,%1\;move%.l %0,%3\;subx%.l %2,%3\;move%.l %3,%0\";
-} ")
-
-(define_insn "subdi3"
-  [(set (match_operand:DI 0 "general_operand" "=d,d,d,<")
-       (minus:DI (match_operand:DI 1 "general_operand" "0,0,0,0")
-                (match_operand:DI 2 "general_operand" "*ao,>,d,<")))]
-  ""
-  "*
-{
-  if (which_alternative == 3)
-    return \"sub%.l %2,%0\;subx%.l %2,%0\";
-  operands[1] = gen_rtx (REG, SImode, REGNO (operands[0]) + 1);
-  if (which_alternative == 1)
+  else if (GET_CODE (operands[0]) == MEM)
     {
+      if (GET_CODE (operands[2]) == MEM
+         && GET_CODE (XEXP (operands[2], 0)) == PRE_DEC)
+       return \"sub%.l %2,%0\;subx%.l %2,%0\";
       CC_STATUS_INIT;
-      return \"neg%.l %0\;add%.l %2,%0\;sub%.l %2,%1\;negx%.l %0\";
+      if (GET_CODE (XEXP (operands[0], 0)) == POST_INC)
+       {
+         operands[1] = gen_rtx (MEM, SImode,
+                  gen_rtx (PLUS, VOIDmode, XEXP(operands[0], 0),
+                           gen_rtx (CONST_INT, VOIDmode, -8)));
+         return \"move%.l %0,%3\;sub%.l %R2,%0\;subx%.l %2,%3\;move%.l %3,%1\";
+       }
+      else if (GET_CODE (XEXP (operands[0], 0)) == PRE_DEC)
+       {
+         operands[1] = XEXP(operands[0], 0);
+         return \"sub%.l %R2,%0\;move%.l %0,%3\;subx%.l %2,%3\;move%.l %3,%1\";
+       }
+      else
+       {
+         operands[1] = adj_offsettable_operand (operands[0], 4);
+         return \"sub%.l %R2,%1\;move%.l %0,%3\;subx%.l %2,%3\;move%.l %3,%0\";
+       }
     }
-  if (GET_CODE (operands[2]) == REG)
-    operands[3] = gen_rtx (REG, SImode, REGNO (operands[2]) + 1);
-  else
-    operands[3] = adj_offsettable_operand (operands[2], 4);
-  if (which_alternative == 2)
-    return \"sub%.l %3,%1\;subx%.l %2,%0\";
-  CC_STATUS_INIT;
-  /* neg + negx simulates (non-existent) subx #0 */
-  /* TODO : this should work also for CONST operands[2] */
-  return \"neg%.l %0\;sub%.l %3,%1\;negx%.l %0\;sub%.l %2,%0\";
 } ")
 
 (define_insn "subsi3"