Add 2 config flags that were missing; make data cache instructions be nops

diff --git a/sim/ppc/ChangeLog b/sim/ppc/ChangeLog
index 58cb18f01f657e632b2fce128117f44547cab0c2..67011519b442123e94e7a143371e0e160efcfb65 100644 (file)
--- a/sim/ppc/ChangeLog
+++ b/sim/ppc/ChangeLog
@@ -1,3 +1,11 @@
+Fri Nov  3 11:37:24 1995  Michael Meissner  <meissner@tiktok.cygnus.com>
+
+       * ppc-instructions (data cache instructions): Make all data cache
+       instructions nops instead of invalid instructions.
+
+       * Makefile.in (CONFIG_CFLAGS): Add ALIGNMENT_CFLAGS and
+       TIMEBASE_CFLAGS which weren't included.
+
 Thu Nov  2 08:54:04 1995  Michael Meissner  <meissner@tiktok.cygnus.com>
 
        * Makefile.in: Uncomment built file dependencies.

diff --git a/sim/ppc/Makefile.in b/sim/ppc/Makefile.in
index e72045844bcf017d9743bd012161558972212bd7..b56e6e50d794794f8d7bcbbf4e2197df70965217 100644 (file)
--- a/sim/ppc/Makefile.in
+++ b/sim/ppc/Makefile.in
@@ -88,6 +88,8 @@ CONFIG_CFLAGS = $(BSWAP_CFLAGS) \
   $(BITSIZE_CFLAGS) \
   $(HOSTBITSIZE_CFLAGS) \
   $(ENV_CFLAGS) \
+  $(TIMEBASE_CFLAGS) \
+  $(ALIGNMENT_CFLAGS) \
   $(FLOAT_CFLAGS) \
   $(TRACE_CFLAGS) \
   $(ASSERT_CFLAGS) \

diff --git a/sim/ppc/ppc-instructions b/sim/ppc/ppc-instructions
index 2fa9c6b448f961f0677db3ceabd9816cac8640ab..8d2ca05df728b4c8cf4830fc671d2911b2223afe 100644 (file)
--- a/sim/ppc/ppc-instructions
+++ b/sim/ppc/ppc-instructions
@@ -2297,10 +2297,19 @@ void::function::invalid_arithemetic_operation:cpu *processor, unsigned_word cia,
 #
 
 0.31,6./,11.RA,16.RB,21.278,31./:X:::Data Cache Block Touch
+       ;       /* nop for now */
+
 0.31,6./,11.RA,16.RB,21.246,31./:X:::Data Cache Block Touch for Store
+       ;       /* nop for now */
+
 0.31,6./,11.RA,16.RB,21.1014,31./:X:::Data Cache Block set to Zero
+       ;       /* nop for now */
+
 0.31,6./,11.RA,16.RB,21.54,31./:X:::Data Cache Block Store
+       ;       /* nop for now */
+
 0.31,6./,11.RA,16.RB,21.86,31./:X:::Data Cache Block Flush
+       ;       /* nop for now */
 
 #
 # II.3.3 Envorce In-order Execution of I/O Instruction