Fix documentation for CLWB ISA.

gcc/
	* doc/invoke.texi (Skylake Server): Add CLWB.
	Cannonlake): Remove CLWB.

From-SVN: r258587

diff --git a/gcc/ChangeLog b/gcc/ChangeLog
index 57e92ac762af037649509c3cc5039781c3d60c60..9ed11727444a5df41b49582e8f453113d9c442fe 100644 (file)
--- a/gcc/ChangeLog
+++ b/gcc/ChangeLog
@@ -1,3 +1,8 @@
+2018-03-16  Julia Koval  <julia.koval@intel.com>
+
+       * doc/invoke.texi (Skylake Server): Add CLWB.
+       Cannonlake): Remove CLWB.
+
 2018-03-16  Jakub Jelinek  <jakub@redhat.com>
 
        PR tree-optimization/84841

diff --git a/gcc/doc/invoke.texi b/gcc/doc/invoke.texi
index 8354d47bc8a4c9dc76372cfde781fd703a263d3a..aca9c8dcebe4851a676a29c6b6bd119853095478 100644 (file)
--- a/gcc/doc/invoke.texi
+++ b/gcc/doc/invoke.texi
@@ -26550,14 +26550,14 @@ AVX5124VNNIW, AVX5124FMAPS and AVX512VPOPCNTDQ instruction set support.
 Intel Skylake Server CPU with 64-bit extensions, MOVBE, MMX, SSE, SSE2, SSE3,
 SSSE3, SSE4.1, SSE4.2, POPCNT, PKU, AVX, AVX2, AES, PCLMUL, FSGSBASE, RDRND, FMA,
 BMI, BMI2, F16C, RDSEED, ADCX, PREFETCHW, CLFLUSHOPT, XSAVEC, XSAVES, AVX512F,
-AVX512VL, AVX512BW, AVX512DQ and AVX512CD instruction set support.
+CLWB, AVX512VL, AVX512BW, AVX512DQ and AVX512CD instruction set support.
 
 @item cannonlake
 Intel Cannonlake Server CPU with 64-bit extensions, MOVBE, MMX, SSE, SSE2,
 SSE3, SSSE3, SSE4.1, SSE4.2, POPCNT, PKU, AVX, AVX2, AES, PCLMUL, FSGSBASE,
 RDRND, FMA, BMI, BMI2, F16C, RDSEED, ADCX, PREFETCHW, CLFLUSHOPT, XSAVEC,
 XSAVES, AVX512F, AVX512VL, AVX512BW, AVX512DQ, AVX512CD, AVX512VBMI,
-AVX512IFMA, SHA, CLWB and UMIP instruction set support.
+AVX512IFMA, SHA and UMIP instruction set support.
 
 @item icelake-client
 Intel Icelake Client CPU with 64-bit extensions, MOVBE, MMX, SSE, SSE2,